Cmsemicon SC8F577 Series - Page 70

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8.3 TIMER0 Related Register
There are two registers related to TIMER0, 8-bit timer/counter (TMR0), and 8-bit programmable control
register (OPTION_REG).
TMR0 is an 8-bit readable and writable timer/counter, OPTION_REG is an 8-bit write-only register, the
user can change the value of OPTION_REG to change the working mode of TIMER0, etc. Please refer to the
application of 0 prescaler register (OPTION_REG).
8-bit timer/counter TMR0 (01H)
01H
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TMR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value
X
X
X
X
X
X
X
X
OPTION_REG register (81H)
81H
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
OPTION_REG
----
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Read/write
----
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value
----
1
1
1
1
0
1
1
Bit7
Not used
Bit6
INTEDG:
Interrupt edge selection bit.
1=
The rising edge of the INT pin triggers interrupt.
0=
The falling edge of the INT pin triggers interrupt.
Bit5
T0CS:
1=
0=
TMR0 clock source selection bit.
Transition edge of T0CKI pin.
Internal instruction period clock (
F
CPU).
Bit4
T0SE:
1=
0=
TIMER0 clock source edge selection bit.
Increment when the T0CKI pin signal transitions from high to low.
Increment when the T0CKI pin signal transitions from low to high.
Bit3
PSA:
1=
0=
pre-scaler allocation bit.
pre-scaler allocated to WDT.
pre-scaler allocated toTIMER0 mod.
Bit2~Bit0
PS2~PS0:
Pre-allocated parameter configuration bits.
PS2
PS1
PS0
TMR0
Frequency
division ratio
WDT Frequency
division ratio
(WDT_DIV=DISABLE)
WDT Frequency
division ratio
(WDT_DIV=ENABLE)
0
0
0
1:2
1:1
1:3
0
0
1
1:4
1:2
1:6
0
1
0
1:8
1:4
1:12
0
1
1
1:16
1:8
1:24
1
0
0
1:32
1:16
1:48
1
0
1
1:64
1:32
1:96
1
1
0
1:128
1:64
1:192
1
1
1
1:256
1:128
1:384