Cmsemicon SC8F577 Series - Page 92

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EEPROM data register EEDATH (8FH)
8FH
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
EEDATH
EEDATH7
EEDATH6
EEDATH5
EEDATH4
EEDATH3
EEDATH2
EEDATH1
EEDATH0
read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
value
X
X
X
X
X
X
X
X
Bit7~Bit0
EEDATH<7:0>:
The upper 8 bits of data read from the program EEPROM/program memory.
EEPROM address register EEADRH (96H)
96H
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
EEADRH
---
---
---
---
EEADRH3
EEADRH2
EEADRH1
EEADRH0
read/write
---
---
---
---
R/W
R/W
R/W
R/W
reset value
---
---
---
---
0
0
0
0
Bit7~Bit5
not used, read 0.
Bit4~Bit0
EEADRH<3:0>:
Specify the upper 5 address of the program memory read operation.
EEPROM control register EECON1 (8CH)
8CH
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
EECON1
EEPGD
---
---
EETIME
WRERR
WREN
WR
RD
read/write
R/W
---
---
R/W
R/W
R/W
R/W
R/W
Reset
value
0
---
---
0
X
0
0
0
Bit7
EEPGD:
Program/program EEPROM selection bit；
1=
Operate program memory；
0=
Operate program EEPROM.
Bit6~Bit5
not used
Bit4
EETIME:
The longest programming waiting time
1=
10ms; (Recommended value)
0=
5ms.
Bit3
WRERR:
EEPROM error flag bit；
1=
Write error (any WDT reset or under voltage reset during normal operation, or the time
set by EETIME is up but the self-check has not been successful);
了)；
0=
Write complete.
Bit2
WREN:
EEPROM write enable bit；
1=
Enable write period；
0=
Disable write memory.
Bit1
WR:
Write control bit；
1=
Start write period (Once the write operation is completed, this bit is cleared by
hardware, and the WR bit can only be set to 1, but not cleared by software);；
0=
Write period complete.
Bit0
RD:
Read control bit；
1=
Start the memory read operation (the RD is cleared by hardware, and the RD bit can
only be set to 1, but not cleared by software);
0=
Not start memory read operation.