Curtiss-Wright GT200 - Page 6

TABLE OF CONTENTS
4.2.11 Throughput .......................................................................................................... 4-4
4.2.12 Message Ordering................................................................................................ 4-4
4.2.13 Memory ............................................................................................................... 4-4
4.2.14 FIFO Buffers........................................................................................................ 4-4
4.2.14.1 Retransmit FIFO ............................................................................... 4-4
4.2.14.2 Receive FIFO.................................................................................... 4-5
4.2.15 Network Status Messaging .................................................................................. 4-5
4.2.15.1 Shared Information ........................................................................... 4-5
4.2.16 Interrupts.............................................................................................................. 4-5
4.2.17 Modes of Operation ............................................................................................. 4-6
4.2.17.1 Write-Me-Last Mode ........................................................................ 4-6
4.2.17.2 TX Enable......................................................................................... 4-6
4.2.17.3 RX Enable......................................................................................... 4-6
4.2.17.4 RT Enable ......................................................................................... 4-6
4.2.17.5 Interrupt Self ..................................................................................... 4-7
4.3 GT200 Block Diagram ............................................................................................................. 4-8
4.3.1 Network Logic....................................................................................................... 4-8
4.3.2 Host Logic ............................................................................................................. 4-8
4.4 Host Hardware.......................................................................................................................... 4-9
4.4.1 Target Interface...................................................................................................... 4-9
4.4.1.1 Control plane....................................................................................... 4-9
4.4.1.2 Data plane. .......................................................................................... 4-9
4.4.2 Initiator Interface ................................................................................................... 4-9
4.4.2.1 Data Plane........................................................................................... 4-9
4.4.3 Bus Support ........................................................................................................... 4-9
4.4.4 5-Volt PCI Bus Support......................................................................................... 4-9
4.4.5 Byte Swapping....................................................................................................... 4-9
4.4.6 Interrupt Support.................................................................................................... 4-9
4.4.7 Counter/Timers.................................................................................................... 4-10
APPENDICES
APPENDIX A SPECIFICATIONS ............................................................................................................. A-1
APPENDIX B COUNTER/TIMER DEFINITIONS.................................................................................... B-1
GLOSSARY ............................................................................................................................... GLOSSARY-1
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