Cypress CY8CKIT-059 PSoC 5LP Prototyping Kit - Page 27

CY8CKIT-059 PSoC® 5LP Prototyping Kit Guide, Doc. #: 001-96498 Rev. *G 27
Hardware
4.2.5.3 Functionality of J8 and J9 Headers (KitProg)
The KitProg board contains two dual-inline headers (J8 and J9). These headers are both 1x7-pin-
headers, used to pull out several pins of PSoC 5LP to support advanced features like a low-speed
oscilloscope and a low-speed digital logic analyzer. This header also contains the KitProg bridge
pins that can be used when the two boards are separated.
The J8 and J9 headers support 100-mil spacing, so you can solder connectors to connect the
KitProg board to any development breadboard.
Figure 4-7. J8 and J9 Headers
Table 4-5. Pin Details of J9 Table 4-6. Pin Details of J8
KitProg GPIO Header (J9)
Pin Signal Description
J9_01 VBUS Power
J9_02 GND Ground
J9_03 P12.5 GPIO
J9_04 P12.0 GPIO/I2C_SCL
J9_05 P12.1 GPIO/I2C_SDA
J9_06 P12.6 GPIO/UART_RX
J9_07 P12.7 GPIO/UART_TX
KitProg GPIO Header (J8)
Pin Signal Description
J8_01 GND Ground
J8_02 P3.0 GPIO
J8_03 P3.4 GPIO
J8_04 P3.5 GPIO
J8_05 P3.6 GPIO
J8_06 P0.0 GPIO
J8_07 P0.1 GPIO