CY8CKIT-059 PSoCĀ® 5LP Prototyping Kit Guide, Doc. #: 001-96498 Rev. *G 26
Hardware
4.2.5.2 Functionality of J7 and J3 Headers (PSoC 5LP to KitProg)
The KitProg and target boards each contain a 1x5-pin header. These headers provide a physical
connection between the two devices. Specifically, the connection includes the SWD interface,
required to program/debug the target PSoC 5LP device, power, ground, and reset.
Figure 4-6. J7 and J3 Headers
When the boards are separated, the KitProg board can be used to program any other PSoC 3,
PSoC 4, or PSoC 5LP family of devices via J7.
Table 4-3. Pin Details of J7 Header Table 4-4. Pin Details of J3 Header
PSoC 5LP to KitProg Header (J7)
Pin Signal Description
J7_01 VTARG Power
J7_02 GND Ground
J7_03 P12.4 RESET
J7_04 P12.3 SWDCLK
J7_05 P12.2 SWDIO
PSoC 5LP (Target) Program and Debug Header (J3)
Pin Signal Description
J3_01 VTARG Power
J3_02 GND Ground
J3_03 XRES RESET
J3_04 P1.1 SWDCLK
J3_05 P1.0 SWDIO
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