Cypress EZ-USB FX3 SDK - Page 52

Cypress EZ-USB® FX3™ SDK Quick Start Guide, Version 1.3.1 52
Once the PLL clock frequency has been generated, the Output Pixel Clock
(PCLK) and CSI RX clock frequency can be obtained by selecting the
appropriate divider value as shown in the image below.
Figure 7-9: Clock Dividers
To configure the MCLK, select Enabled from the MClk dropdown box to enable
configuration of the MCLK related dividers.
Figure 7-10: MCLK Settings
Select a MClkDiv value and then change MClkLow and MClkHigh values to
achieve the desired MCLK frequency
Figure 7-11: MCLK Dividers
The Data Format field is used to determine the pixel width and format as
described in Section 7.2.2 above; and the Fifo Delay field is used to set a
threshold of pixels to be met before data output on the parallel interface is
started.
Figure 7-12: Output Data Format Selection
6. Managing Errors in the Configuration Data
If an individual field violates permitted minimum or maximum values, it is
highlighted in a RED color as shown in the following image and a small RED x
mark is shown to the right of the input box. Hovering over the x will show the
user the permitted values for the field.