ADV-700
38
SDOS 1
I2C 2
SMUTE 3
BICK 4
LRCK 5
SDTI1 6
SDTI2 7
SDTI3 8
SDTO 9
DAUX 10
DFS
DZF2/OVF
RIN+
RIN-
LIN+
LIN-
ROUT1
LOUT1
ROUT2
LOUT2
ROUT3
LOUT311
NC 12
DZFE 13
TVDD 14
DVDD 15
DVSS 16
PDN 17
TST 18
NC 19
ADIF 20
CAD1 21
CAD0 22
33
32
31
30
29
28
27
26
25
24
23
LOOP1
LOOP0/SDA/CDTI
DIF1/SCL/CCLK
DIF0/CSN
P/S
MCLK
DZF1
AVSS
AVDD
VREFH
VCOM
44
43
42
41
40
39
38
37
36
35
34
AK4527BVQ
Top View
AK4527BVQ Terminal Funtion
AK4527BVQ (DS: IC108)
1 SDOS I SDTO source select pin, L: Internal ADC output, H: DAUX input
2 I2C I Serial control mode select pin, L: 3-core serial, H: I
2
C bus
3 SMUTE I Soft mute pin, H: Soft mute start, L: Release
4 BICK I Audio serial data clock pin
5 LRCK I Input channel clock pin
6 SDTI1 I DAC1 audio serial data input pin
7 SDTI2 I DAC2 audio serial data input pin
8 SDTI3 I DAC3 audio serial data input pin
9 SDTO O Audio serial data output pin
10 DAUX I Auxiliary audio serial data input pin
11 DFS I Double speed sampling mode pin, L: Normal, H: Double
12 NC No connection
13 DZFE I Zero input detect function activate pin, L: Mode 7 at parallel, H: Mode 0
14 TVDD Power pin for output buffer, 2.7V~5.5V
15 DVDD Digital power pin, 4.5V~5.5V
16 DVss Digital GND pin, 0V
17 PDN I Power down & reset pin, L: Powered-down and register initialized, Reset with PDN when switching CAD0-1
18 TST I Test pin, connect to DVSS
19 NC No connection
20 ADIF I Analog input type select pin, H: Differential, L: Single-end
21 CAD1 I Chip address-1 pin
22 CAD0 I Chip address-0 pin
23 LOUT3 O DAC3L channel analog out pin
24 ROUT3 O DAC3R channel analog out pin
25 LOUT2 O DAC2L channel analog out pin
26 ROUT2 O DAC2R channel analog out pin
27 LOUT1 O DAC1L channel analog out pin
28 ROUT1 O DAC1R channel analog out pin
29 LIN- I L-ch analog inverted input pin
30 LIN+ I L-ch analog non-inverted input pin
31 RIN- I R-ch analog inverted input pin
32 RIN+ I R-ch analog non-inverted input pin
33 DZF2/OVF O
0 input detect 2 pin, H: Input data of G2 is 8192 times “0” in a raw or RSTN bit “0”, L: When P/S= “0” /Analog input overflow detect pin
34 VCOM O Common V-out pin, AVDD/2, connect large capacitor to avoid noise
35 VREFH I Ref. V input pin, AVDD
36 AVDD Analog GND pin, 4.5V~5.5V
37 AVss Analog GND pin, 0V
38 DZF1 O 0 input detect pin, H: Input data of G1 is 8192 times “0” in a raw or RSTN bit “0”, L: When P/S= “0”
39 MCLK I Master clock input pin
40 P/S I Parallel/Serial select pin, L: Serial control
41
DIF0 I Audio data I/F format 0 pin (parallel control)
CSN I Chip select pin (3-wire serial control), connect to DVDD when I
2
C bus control
42
DIF1 I Audio data I/F format 1 pin (parallel control)
SCL/CCLK I Control data clock pin (serial control), I
2
C=”L”: CCLK (3-wire serial), I
2
C=”H”: SCL (I
2
C bus)
43
LOOP0 I Loop back mode 0 pin (parallel control), effects digital loop back ADC to all DAC
SDA/CDTI I/O Control data input pin (serial control), I
2
C=”L”: CCTI (3-wire serial), I2C=”H” SDA (I
2
C bus)
44 LOOP1 I Loop back mode 1 pin, from SDT1 to all DAC
Port Name Function
Pin
No.
I/O
w
w
w
.
x
i
a
o
y
u
1
6
3
.
c
o
m
Q
Q
3
7
6
3
1
5
1
5
0
9
9
2
8
9
4
2
9
8
T
E
L
1
3
9
4
2
2
9
6
5
1
3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com
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