ADV-700
40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DGND
MCLK
CLATCH
CCLK
CDATA
384/256
X2MCLK
ZEROR
DEEMP
96/48
AGND
OUTR+
OUTR
−
FILTR
DVDD
SDATA
BCLK
L/RCLK
PD/RST
MUTE
ZEROL
IDPM0
IDPM1
FILTB
AVDD
OUTL+
OUTL
−
AGND
AD1854 (DS: IC401)
SN74LV00APW
(DS: IC110, 111)
AT49LV002-70TC
(DS: IC101 )
SN74LV4040APW
(DS: IC114)
LC4966
(DS: IC605)
TC74VHC123AFT
(DS: IC123)
1A
1B
1 CLR
1Q
2Q
2Cext
2R
ext / Cext
GND
1
2
3
4
5
6
7
8
CLR
QQ
QQ
CLR
16
15
14
13
12
11
10
9
Vcc
1Rext/Cext
1Cext
1Q
2Q
2CLR
2B
2A
1A
1B
1Y
2A
2B
2Y
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Vcc
4B
4A
4Y
3B
3A
3Y
GND
A11 32 OE1
A9 31 A102
A8 30 CE3
A13 29 I/O74
A14 28 I/O65
A17 27 I/O56
WE 26 I/O47
VCC 25 I/O38
*RESET 24 GND9
A16 23 I/O210
A15 22 I/O111
A12 21 I/O012
A7 20 A013
A6 19 A114
A5 18 A215
A4 17 A316
IN 1
OUT 1
OUT 2
IN 2
CONTROL 2
CONTROL 3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VDD
CONTROL 1
CONTROL 4
IN 4
OUT 4
OUT 3
IN 3
VSS
IN
IN
IN
IN
C
C
C
C
OUT
OUT
OUT
OUT
Outputs
QL
QF
QE
QG
QD
QC
QB
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Vcc
QK
QJ
QH
QI
CLR
CLK
Outputs
Output
QA
QL
QA
QF
QE
QG
QD
QC
QB
QK
QJ
QH
QI
CLR
CLK
Terminal Function
Pin Name
Function
Pin No.
I/O
1 DGND I Digital Ground.
2 MCLK I Master Clock Input.
3 CLATCH I Latch input for control data.
4 CCLK I Control clock input for control data.
5 CDATA I Serial control input.
6 384/256 I Selects the master clock mode.
7 X2MCLK I Selects internal clock doubler (LO) or internal clock=MCLK (HI).
8 ZEROR O Right Channel Zero Flag Output.
9 DEEMP I De-Emphasis.
10 96/48 I Selects 48 kHz (LO) or 96 kHz Sample Frequency Control.
11,15 AGND I Analog Ground.
12 OUTR+ O Right Channel Positive line level analog output.
13 OUTR- O Right Channel Negative line level analog output.
14 FILTR O Voltage Reference Filter Capacitor Connection.
16 OUTL- O Left Channel Negative line level analog output.
17 OUTL+ O Left Channel Positive line level analog output.
18 AVDD I Analog Power supply.
19 FILTB O Filter Capacitor connection.
20 IDPM1 I Input serial data port mode control one.
21 IDPM0 I Input serial data port mode control zero.
22 ZEROL O Left Channel Zero Flag output.
23 MUTE I Mute. Assert HI to mute both stereo analog outputs.
24 PD/RST I Power-Down/Reset.
25 L/RCLK I Left/Right clock input for input data.
26 BCLK I Bit clock input for input data.
27 SDATA I Serial input.
28 DVDD I Digital Power Supply.
w
w
w
.
x
i
a
o
y
u
1
6
3
.
c
o
m
Q
Q
3
7
6
3
1
5
1
5
0
9
9
2
8
9
4
2
9
8
T
E
L
1
3
9
4
2
2
9
6
5
1
3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com
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