Denon ADV-M71 - Page 32

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32
ADV-M71
74VHC573MTCX (DS: IC803,804)
SN74AHCT595PW (MA: IC306)
V
IN
VO
GND
V
C
FRONT
VIEW
PQ018EF01SZ (MA: IC706)
1
2
3
4
5
6
7
8
10
9
20
19
18
17
16
15
14
13
12
11
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
Vcc
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE
D
Q
L
D
Q
L
D
Q
L
D
Q
L
D
Q
L
D
Q
L
D
Q
L
D
Q
L
D0
D1 D2
D3 D4 D5 D6
D7
L
E
OE
1
234
567
89
11
12131415
16
17
1819
Q0 Q1
Q2
Q3
Q4 Q5 Q6 Q7
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
GND
V
CC
Q
A
SER
OE
RCLK
SRCLK
SRCLR
Q
H′
FUNCTION TABLE
INPUTS
FUNCTION
SER SRCLK SRCLR RCLK OE
FUNCTION
X X X X H Outputs Q
A
–Q
H
are disabled.
X X X X L Outputs Q
A
–Q
H
are enabled.
X X L X X Shift register is cleared.
L ↑ H X X
First stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
H ↑ H X X
First stage of the shift register goes high.
Other stages store the data of previous stage, respectively.
X ↓ H X X Shift-register state is not changed.
X XX↑ X Shift-register data is stored in the storage register.
X X X ↓ X Storage-register state is not changed.
logic diagram (positive logic)
3D
C3
1D
C1
R
3D
C3
2D
C2
R
3D
C3
2D
C2
R
3D
C3
2D
C2
R
3D
C3
2D
C2
R
3D
C3
2D
C2
R
3D
C3
2D
C2
R
3D
C3
2D
C2
R
13
12
10
11
14
15
1
2
3
4
5
6
7
9
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
Q
H
OE
SRCLR
RCLK
SRCLK
SER
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
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