Denon AVR-1723 - Page 143

143
H27U1G8F2BTR-BC Block Diagram
Rev 1.1 / Sep. 2009 15
1
H27U1G8F2B Series
1 Gbit (128 M x 8 bit) NAND Flash
Figure 4 : Block Diagram
ADDRESS
REGISTER/
COUNTER
PROGRAM
ERASE
CONTROLLER
HV GENERATION
COMMAND
INTERFACE
LOGIC
COMMAND
REGISTER
DATA
REGISTER
IO
RE
BUFFERS
Y DECODER
PAGE BUFFER
X
D
E
C
O
D
E
R
1024 Mbit + 32 Mbit
NAND Flash
MEMORY ARRAY
WP
CE
WE
CLE
ALE
A27 ~ A0