Denon AVR-390 - Advanced Operations and Adjustments; Recording to an External Device; Adjusting Channel Levels with Test Tone

32
DHT-390XP AVR-390
Sil9185 (IC01)
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
20
AGND
R0XC+
R0XC-
AVCC18
HPD0
LSCL/
EPSEL[1]
LSDA/
EPSEL[0]
RESET#
EXTSWING
TxC-
TxC+
AGND
Tx0-
Tx0+
AVCC18
Tx1-
Tx1+
AGND
Tx2-
Tx2+
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
41
R1X0-
R1X0+
AVCC33
R1X1-
R1X1+
AGND
R1X2-
R1X2+
AVCC18
DSDA1
DSCL1
RPWR1
CEC_D
CEC_A
AVCC33
HPD2
AVCC18
R2XC-
R2XC+
AGND
39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24
23
22 21 40
AGND R1XC+ R1XC- AVCC18 HPD1 I2CSEL/ INT DGND DVCC18 RPWR0 DSCL0 DSDA0 AVCC18 R0X2+ R0X2- AGND R0X1+ R0X1- AVCC33 R0X0+ R0X0-
62
63
64 65 66 67 68 69 70 71 72 73 74 75 76 77
78
79 80
61
R2X0-
R2X0+
AVCC33
R2X1-
R2X1+
TPWR/
AGND
R2X2-
R2X2+
AVCC18
DSDA2
DSCL2
RPWR2
DVCC18
DGND
RSVDL
HPDIN
TSDA
TSCL
I2CADDR
AGND
Sil 9185 Pin Mapping
Sil 9185
80-Pin TQFP
(Top View)
Figure 1. Pin Mapping
BLOCK DIAGRAM
R0X0+/-
R0X1+/-
R0X2+/-
R0XC+/-
R1X0+/-
R1X1+/-
R1X2+/-
R1XC+/-
R2X0+/-
R2X1+/-
R2X2+/-
R2XC+/-
TX0+/-
TX1+/-
TX2+/-
TXC+/-
EPSEL1/
LSCL
EPSEL0/
LSDA
Port0_DDC Port1_DDC Port2_DDC TX_DDC
RPWR0 RPWR1 RPWR2
I2CADDR/
TPWR
HPD0 HPD1 HPD2
HPDIN
CEC_A
CEC_D
Termination/ Termination/
Equalizer
Oversample
DPLL
CEC
Equalizer
Equalizer
Termination/
Config
Logic
EDID Block
EDID
RAM
Transmitter
Configuration Block
Block
Transmit
PLL
CEC I/F
Receiver Block
HPD
Switch
5V Switch
Drivers
I C Switch
2