Denon DRA-100

CY8C20234(IC301)
BlockDiagram
PinDiscription
CY8C20134, CY8C20234, CY8C20334
CY8C20434, CY8C20534, CY8C20634
Document Number: 001-05356 Rev. *Q Page 12 of 48
16-Pin Part Pinout
Figure 5. CY8C20234 16-Pin PSoC Device
Table 5. Pin Definitions – CY8C20234 16-Pin (QFN no e-pad)
Pin No.
Type
Name Description
Digital Analog
1 I/O I P2[5]
2 I/O I P2[1]
3 I
OH
I P1[7]
I
2
C SCL, SPI SS
4 I
OH
I P1[5]
I
2
C SDA, SPI MISO
5 I
OH
I P1[3] SPI CLK
6 I
OH
I P1[1]
CLK
[6]
, I
2
C SCL, SPI MOSI
7 Power V
SS
Ground connection
8 I
OH
I P1[0]
DATA
[6]
, I
2
C SDA
9 I
OH
I P1[2]
10 I
OH
I P1[4] Optional external clock input (EXTCLK)
11 Input XRES Active high external reset with internal pull-down
12 I/O I P0[4]
13 Power V
DD
Supply voltage
14 I/O I P0[7]
15 I/O I P0[3] Integrating Input
16 I/O I P0[1]
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive
QFN
(Top View)
AI, P2[5]
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
AI, SPI CLK, P1[3]
1
2
3
4
11
10
9
16 15 14
13
P0[3], AI P0[7], AI V
DD
P0[4], AI
CLK, I2C SCL, SPI MOSI P1[1]
AI, DATA, I2C SDA, P1[0]
P1[2], AI
AI, P2[1]
P1[4], AI, EXTCLK
XRES
P0[1], AI
V
SS
12
5 6 7 8
Note
6. These are the ISSP pins, that are not High Z at POR (Power-on-Reset). See the PSoC Technical Reference Manual for details.
CY8C20134, CY8C20234, CY8C20334
CY8C20434, CY8C20534, CY8C20634
PSoC
®
Programmable System-on-Chip™
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-05356 Rev. *Q Revised June 15, 2012
PSoC
®
Programmable Sys tem-on-Chip™
Features
■ Low power CapSense
®
block
❐ Configurable capacitive sensing elements
❐ Supports combination of CapSense buttons, sliders,
touchpads, and proximity sensors
■ Powerful Harvard-architecture processor
❐ M8C processor speeds running up to 12 MHz
❐ Low power at high speed
❐ Operating voltage: 2.4 V to 5.25 V
❐ Industrial temperature range: –40 °C to +85 °C
■ Flexible on-chip memory
❐ 8 KB flash program storage 50,000 erase/write cycles
❐ 512-Bytes SRAM data storage
❐ Partial flash updates
❐ Flexible protection modes
❐ Interrupt controller
❐ In-system serial programming (ISSP)
■ Complete development tools
❐ Free development tool (PSoC Designer™)
❐ Full-featured, in-circuit emulator, and programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128 KB trace memory
■ Precision, programmable clocking
❐ Internal ±5.0% 6- / 12-MHz main oscillator
❐ Internal low speed oscillator at 32 kHz for watchdog and sleep
■ Programmable pin configurations
❐ Pull-up, high Z, open-drain, and CMOS drive modes on all
GPIOs
❐ Up to 28 analog inputs on all GPIOs
❐ Configurable inputs on all GPIOs
❐ 20-mA sink current on all GPIOs
❐ Selectable, regulated digital I/O on port 1
• 3.0 V, 20 mA total port 1 source current
• 5 mA strong drive mode on port 1 versatile analog mux
❐ Common internal analog bus
❐ Simultaneous connection of I/O combinations
❐ Comparator noise immunity
❐ Low-dropout voltage regulator for the analog array
■ Additional system resources
❐ Configurable communication speeds
•I
2
C: selectable to 50 kHz, 100 kHz, or 400 kHz
• SPI: configurable between 46.9 kHz and 3 MHz
❐ I
2
C slave
❐ SPI master and SPI slave
❐ Watchdog and sleep timers
❐ Internal voltage reference
❐ Integrated supervisory circuit
SR AM
512 Bytes
System Bus
Interrupt
Controller
6/12 MHz Internal Main Oscillator
Global Analog Interconnect
PSoC
CORE
CPU Core
(M8 C )
SROM Flash 8K
SYSTEM RESOURCES
ANALOG
SYSTEM
Analog
Ref.
I2C Slave/SPI
Master-Slave
POR and LVD
System Res ets
Port 1 Port 0
Sleep and
Watchdog
Analog
Mux
Port 3 Port 2
CapSense
Block
Config LDO
Logic Block Diagram
Pin No.
Type
Name Description
Digital Analog
1 I/O I P2[5]
2 I/O I P2[1]
3 I
OH
I P1[7]
I
2
C SCL, SPI SS
4 I
OH
I P1[5]
I
2
C SDA, SPI MISO
5 I
OH
I P1[3] SPI CLK
6 I
OH
I P1[1]
CLK
[6]
, I
2
C SCL, SPI MOSI
7 Power V
SS
Ground connection
8 I
OH
I P1[0]
DATA
[6]
, I
2
C SDA
9 I
OH
I P1[2]
10 I
OH
I P1[4] Optional external clock input (EXTCLK)
11 Input XRES Active high external reset with internal pull-down
12 I/O I P0[4]
13 Power V
DD
Supply voltage
14 I/O I P0[7]
15 I/O I P0[3] Integrating Input
16 I/O I P0[1]
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive
79