Denon DRA-100

TPS562200(IC1001,IC1014,IC1012)
BlockDiagram
SW
VBST
VFB
GND
2
3
1
EN
4
6
5
VIN
TPS562200 , TPS563200
www.ti.com SLVSCB0B –JANUARY 2014 – REVISED AUGUST 2014
6 Pin Configuration and Functions
TPS562200, TPS563200
DDC Package
Top View
Pin Functions
PIN
DESCRIPTION
NAME NUMBER
Ground pin Source terminal of low-side power NFET as well as the ground terminal for controller circuit.
GND 1
Connect sensitive VFB to this GND at a single point.
SW 2 Switch node connection between high-side NFET and low-side NFET.
VIN 3 Input voltage supply pin. The drain terminal of high-side power NFET.
VFB 4 Converter feedback input. Connect to output voltage with feedback resistor divider.
EN 5 Enable input control. Active high and must be pulled up to enable the device.
VBST 6 Supply input for the high-side NFET gate drive circuit. Connect a 0.1µF capacitor between VBST and SW pins.
Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: TPS562200 TPS563200
2 SW
ZC
XCON
PWM
Control Logic
+
+
+
UVP
OVP
3 VIN
Ton
One-Shot
6
VBST
+
4
VFB
OCL
+
+
Soft Start
5EN
HS
LS
1 GND
SS
Voltage
Reference
Ref
Hiccup
V
UVP
V
OVP
OCL
threshold
Regulator
UVLO
VREG5
VREG5
TSD
TPS562200 , TPS563200
SLVSCB0B –JANUARY 2014 – REVISED AUGUST 2014 www.ti.com
8 Detailed Description
8.1 Overview
The TPS562200 and TPS563200 are 2-A and 3-A synchronous step-down converters. The proprietary D-
CAP2™mode control supports low ESR output capacitors such as specialty polymer capacitors and multi-layer
ceramic capacitors without complex external compensation circuits. The fast transient response of D-CAP2™
mode control can reduce the output capacitance required to meet a specific level of performance.
8.2 Functional Block Diagrams
Figure 19. Functional Block Diagram: TPS562200 and TPS563200
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Product Folder Links: TPS562200 TPS563200
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