Denon DRA-F107 - Page 20

20
DRA-F107 / DRA-F107DAB
SEMICONDUCTORS
Only major semiconductors are shown, general semiconductors etc. are omitted to list.
The semiconductor which described a detailed drawing in a schematic diagram are omitted to list.
1. IC’s
M3062LFGPGP (IC62)
M3062LFGPGP Terminal Function
Pin
No.
Port
Function
Port
setting
Port Name Explaanation
Output of
Standby &
Default
1 P94 O [LED_RL] [STANDBY Red LED output. ON:High] L
2 P93 O FL RESET Reset output to FLD L
3 TB2IN I FUNC_JOGB FUNCTION encoder Pulse-B input HI-Z
4 P91 O Not Used:N.C. L
5 TB0IN I FUNC_JOGA FUNCTION encoder Pulse-A input HI-Z
6 BYTE (VSS) GND -
7 CNVSS I FLASH CNVss Select input of Flash rom write mode HI-Z
8 P87 O Not Used:N.C. L
9 P86 O Not Used:N.C. L
10 RESET I RESET Reset input HI-Z
11 XOUT XTAL(16MHz) Xtal output -
12 VSS (VSS) GND -
13 XIN XTAL(16MHz) Xtal input -
14 VCC (VCC) Positive power -
15 NMI I (PullUp) Pull up HI-Z
16 P84 O Not Used:N.C. L
17 INT1 INT POWER KEY Power button input (interrupt input) HI-Z
18 INT0 INT /DBRXD DENON BUS Data input (interrupt input) HI-Z
19 P81 I 50/60 50Hz/60Hz AC Input HI-Z
20 P80 I H/P SW HEAD PHONE insert detect signal input HI-Z
21 TA3IN I VOL JOGB VOL encoder Pulse-B input HI-Z
22 TA3OUT I VOL JOGA VOL encoder Pulse-A input HI-Z
23 P75 O FLCS Chip Select output to FLD L
24 P74 O LED G POWER/SANDBY Green LED output. ON:High L
25 P73 O LED R POWER/SANDBY Red LED output. ON:High L
26 CLK2 O /DBCLK(DENON BUS) Serial Clock output for DENON BUS H
27 RXD2 I /DBRXD(DENON BUS) Serial Data input for DENON BUS HI-Z
75
76
1
100
51
50
26
25