Functional Description
controller is implemented to avoid mistriggering by the
ring after MOSFET is turned off. Functionality of these
parts is described as in the following.
3.3.1.1 Up/down Counter
The up/down counter stores the number of zero
crossing to be ignored before the main power switch is
switched on after demagnetisation of the transformer.
This value is a function of the regulation voltage, which
contains information about the output power.
Generally, a high output power results in a high
regulation voltage. According to this information, the
value in the up/down counter is changed to a low value
in case of high regulation voltage, and to a high value
in case of low regulation voltage. In ICE2QS01, the
lowest value of the counter is 1 and the highest 7.
Following text explains how the up/down counter value
changes in responding to the regulation voltage v
REG
.
The regulation voltage v
REG
is internally compared with
three thresholds V
RL
, V
RH
and V
RM
. According to the
results, the value in the up/down counter is changed,
which is summarised in Table 1 and Figure 4
respectively.
Table 1 Operation of the up/down counter
Figure 4 Up/down counter operation
According to the comparison results the up/down
counter counts upwards, keeps unchanged or counts
downwards. However, the value in up/down counter is
limited between 1 and 7. If the counter tends to count
beyond this range, the attempt is ignored.
In normal case, the up/down counter can only be
changed by one each time at the clock period of 48ms.
However, to ensure a fast response to sudden load
increase, the counter is set to 1 in the following
switching period after the regulation voltage v
REG
exceeds the threshold V
RM
.
3.3.1.2 Zero-Crossing Counter and Ringing
Suppression Time Controller
In the system, the voltage from the auxiliary winding is
applied to the zero-crossing pin through a RC network,
which provides a time delay to the voltage from the
auxiliary winding. Internally, this pin is connected to a
clamping network, a zero-crossing detector, an output
overvoltage (OP OVP) detector and a ringing
suppression time controller.
During on-state of the power switch a negative voltage
applies to the ZC pin. Through the internal clamping
network, the voltage at the pin is clamped to certain
level. However, it is highly recommended that a fast-
recovery diode D
zc
is added to block the negative
voltage when the power switch is on. This is because
the device in MOS technology is sensitive to negative
voltage.
The voltage at the ZC pin v
ZC
is compared with the
threshold V
ZCT1
. Once the voltage v
ZC
crosses the
threshold at its falling edge, a pulse is generated which
is fed to the zero-crossing counter and the counter
value increases by 1.
After MOSFET is turned on, there will be some
oscillation on V
DS
, which will also appear on the voltage
on ZC pin. To avoid the MOSFET is turned on
mistriggerred by such oscillation, a ringing suppression
timer is implemented. The time is dependent on the
voltage v
ZC
. When the voltage v
ZC
is lower than the
threshold V
ZCT2
, a longer preset time applies, while a
shorter time is set when the voltage v
ZC
is higher than
the threshold.
The voltage v
ZC
is used for the output overvoltage
protection, as well. Once the voltage at this pin is
higher than the threshold V
OPOVP
during off-time of the
main switch, the IC is latched off after a fixed blanking
time.
To achieve the switch-on at voltage valley, the voltage
from the auxiliary winding is fed to a time delay network
(the RC network consists of D
zc
, R
zc1
, R
zc2
and C
zc
as
shown in typical application circuit) before it is applied
to the zero-crossing detector through the ZC pin. The
needed time delay to the main oscillation signal 't
should be approximately one fourth of the oscillation
period (by transformer primary inductor and drain-
source capacitor) minus the propagation delay from the
v
REG
up/down counter
action
Always lower than V
RL
Count upwards till
7
Once higher than V
RL
, but
always lower than V
RH
Stop counting, no
value changing
Once higher than V
RH
, but
always lower than V
RM
Count downwards
till 1
Once higher than V
RM
Set up/down
counter to 1
1Case 3
Case 2
Case 1
n
n+1
n+2
n+2
n+2
n+2
n+1
n
n-1
4 5 6 6 6 6 5 4 3
1
1
2 3 4 4 4 4 3 2 1
7 7 7 7 7 7 6 5 4
t
t
V
FB
V
RM
V
RH
V
RL
clock T=48ms
1
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