Denon PMA-2500NE - Page 63

M3062LFGPGP (DIGITAL: U102)
Block Diagram
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57585960616263646566676869707172737475
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1
00
P0 0 /AN 00 /D 0
P0 1 /AN 01 /D 1
P0 2 /AN 02 /D 2
P0 3 /AN 03 /D 3
P0 4 /AN 04 /D 4
P0 5 /AN 05 /D 5
P0 6 /AN 06 /D 6
P0 7 /AN 07 /D 7
P1 0 /D 8
P1 1 /D 9
P1 2 /D 10
P1
3
/D
11
P1
4
/D
12
V REF
AV SS
V
CC1
X
IN
X
OUT
V
SS
RESET
CNVss
P8
7
/X
CIN
P8
6
/X
COUT
BYTE
P2
0
/AN
20
/A
0
(/D
0
/-)
P2
1
/AN
21
/A
1
(/D
1
/D
0
)
P2
2
/AN
22
/A
2
(/D
2
/D
1
)
P2
3
/AN
23
/A
3
(/D
3
/D
2
)
P2
4
/AN
24
/A
4
(/D
4
/D
3
)
P2
5
/AN
25
/A
5
(/D
5
/D
4
)
P2
6
/AN
26
/A
6
(/D
6
/D
5
)
P2
7
/AN
27
/A
7
(/D
7
/D
6
)
P3
0
/A
8
(/-/D
7
)
P3
1
/A
9
P3
2
/A
10
P3
3
/A
11
P3
4
/A
12
P3
5
/A
13
P3
6
/A
14
P3
7
/A
15
P4
0
/A
16
P4
1
/A
17
P4 2 /A 18
P4 3 /A 19
P7
4
/TA2
OUT
/W
P7
6
/TA3
OUT
P5 6 /ALE
P7
7
/TA3
IN
P5 5 /HOLD
P5 4 /HLDA
P5 3 /BCLK
P5
2 /RD
V
CC2
V
SS
P5 7 /RDY/CLK OUT
P4 5 /CS1
P4 6 /CS2
P4 7 /CS3
AVcc
P6 3 /T X D 0 /SDA 0
P6 5 /CLK 1
P6 6 /RxD 1 /SCL 1
P6 7 /T X D 1 /SDA 1
P6 1 /CLK 0
P6 2 /RxD 0 /SCL 0
P10 0 /AN 0
P10 1 /AN 1
P10 2 /AN 2
P10 3 /AN 3
P9
3
/DA
0
/TB3
IN
P9
4
/DA
1
/TB4
IN
P9 5 /ANEX0/CLK4
P9
6 /ANEX1/S OUT 4
P9
1
/TB1
IN
/S
IN
3
P9
2
/TB2
IN
/S
OUT
3
P8
0
/TA4
OUT
/U
P6 0 /CTS 0 /RTS 0
P6 4 /CTS 1 /RTS 1 /CTS 0 /CLKS 1
P8
2
/INT
0
P8
3
/INT
1
P8
5
/NMI
P9 7 /AD TRG /S IN 4
P4 4 /CS0
P5 0 /WRL/WR
P5 1 /WRH/BHE
P9
0
/TB0
IN
/CLK3
P8
4
/INT
2
P7 2 /CLK 2 /TA1 OUT /V
P7
1 /RxD 2 /SCL 2 /TA0 IN /TB5 IN (Note)
P7
0 /T X D 2 /SDA 2 /TA0 OUT (Note)
P7
5
/TA2
IN
/W
P
7
3
/CTS
2
/RTS
2
/TA1
IN
/V
P1
5
/D
13
/INT
3
P1
6
/D
14
/INT
4
P1
7
/D
15
/INT
5
P10 7 /AN 7 /KI 3
P10 6 /AN 6 /KI 2
P10 5 /AN 5 /KI 1
P10 4 /AN 4/ KI 0
P8
1
/TA4
IN
/U
M16C/62P Group
PIN CONFIGURATION (top view)
Timer (16-bit)
Output (timer A): 5
Input (timer B): 6
Internal peripheral functions
Watchdog timer
(15 bits)
DMAC
(2 channels)
D-A converter
(8 bits X 2 channels)
A-D converter
(10 bits X 8 channels
Expandable up to 26 channels)
UART or
clock synchronous serial I/O
(8 bits X 3 channels)
System clock generator
X
IN -X OUT
X CIN -X COUT
PLL frequency synthesizer
Ring oscillator
M16C/60 series16-bit CPU core
Port P0
8
Port P1
8
Port P2
8
Port P3
8
Port P4
8
Port P5
8
Port P6
8
CRC arithmetic circuit (CCITT )
(Polynomial : X
16
+X
12
+X
5
+1)
Memory
8
7
8
8
Port P10
Port P9
Port P8
Port P7
Port P8
5
ROM
(Note 1)
RAM
(Note 2)
Note 1: ROM size depends on microcomputer type.
Note 2: RAM size depends on microcomputer type.
Note 3: Ports P11 to P14 exist only in 128-pin version.
Clock synchronous serial I/O
(8 bits X 2 channels)
R0LR0H
R1H R1L
R2
R3
SB
FLG
USP
ISP
INTB
PC
Multiplier
Port P11
8
Port P14
2
Port P12
8
Port P13
8
Three-phase motor
control circuit
A0
A1
FB
<V CC2 ports>
(Note 3) (Note 3)
(Note 3)
(Note 3)
<V CC1 ports>
<V
CC1
ports>
<V CC1 ports> <V CC2 ports>
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