Denon PMA-2500NE - Page 65

Pin
No.
Pin Name Signal Name I/O Initial Note
60 VCC2 Vcc I - VCC
61 P3_0/A8(/-/D7) NC O L not use
62 VSS GND I - GND
63 P2_7/AN2_7/A7(/D7/D6) DIR1_CIDO I H DIR control (PCM9211)
64 P2_6/AN2_6/A6(/D6/D5) DIR1_CK O L DIR control (PCM9211)
65 P2_5/AN2_5/A5(/D5/D4) DIR1_CE O H DIR control (PCM9211)
66 P2_4/AN2_4/A4(/D4/D3) DIR1_CODI O L DIR control (PCM9211)
67 P2_3/AN2_3/A3(/D3/D2) FS0 O L USB-DAC control
68 P2_2/AN2_2/A2(/D2/D1) FS1 O L USB-DAC control
69 P2_1/AN2_1/A1(/D1/D0) AL32_SIG_SEL O L USB-DAC control
70 P2_0/AN2_0/A0(/D0/-) AL32_EMPHA O L USB-DAC control
71 P1_7/D15/*INT5 USBB_MUTE I H USB-DAC control
72 P1_6/D14/*INT4 USBB_INT_REQ_N I H USBB_INT (DCD-SX11 102pin)
73 P1_5/D13/*INT3 REMOTE (RC5_IN) I - REMOTE IN
74 P1_4/D12 AL32_TEST3 O L FPGA control
75 P1_3/D11 AL32_TEST4 O H FPGA control
76 P1_2/D10 AL32_TEST5 O L FPGA control
77 P1_1/D9 A_MUTE O H AMUTE (Mute for Digital input) (H/L=Mute OFF/ON)
78 P1_0/D8 PCONT (P_ON) O H POWER ON/STANDBY control (H/L=Power ON/OFF)
79 P0_7/AN0_7/D7 MODE(PCM/DSD) O H MCLK select (H/L=DSD/PCM)
80 P0_6/AN0_6/D6 NC O L not use
81 P0_5/AN0_5/D5 DESTINATION_SEL I -
Auto Standby default setting H/L=Auto Standby
ON/OFF
82 P0_4/AN0_4/D4 VOL_DOWN O L Volume Down
83 P0_3/AN0_3/D3 VOL_UP O L Volume Up
84 P0_2/AN0_2/D2 NC O L not use
85 P0_1/AN0_1/D1 FCEN O H FL Display Chip select
86 P0_0/AN0_0/D0
AD32 Reset (FPGA_
RESERVE1)
O FPGA control
87 P10_7/AN7/*KI3 I2C_SDA I/O USB-DAC control
88 P10_6/AN6/*KI2 I2C_SCL I/O USB-DAC control
89 P10_5/AN5/*KI1 KEY1 (TACT) I - KEY1 (Front tact SW)
90 P10_4/AN4/*KI0 SEL I - Front input Selector SW (A/D input)
91 P10_3/AN3 USBB_RST O USB-DAC control
92 P10_2/AN2 USB-B_DETECT I USB-DAC VBUS detect
93 P10_1/AN1 FPGA_RESERVE2 O FPGA control
94 AVSS AVSS I - GND
95 P10_0/AN0 FPGA_RESERVE3 O FPGA control
96 VREF VREF I - VCC
97 AVCC AVCC I - VCC
98 P9_7/*ADTRG/SIN4 FPGA_RESERVE4 O FPGA control
99 P9_6/ANEX1/SOUT4 FDAT O H FL Display Data
100 P9_5/ANEX0/CLK4 FCLK O H FL Display CLK
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