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MX25L4006EM2I-12G (DIGITAL : U705)
PCM1795 (DAC : U410)
Terminal Function
NAME NO. I/O DESCRIPTION
AGND1 19
AGND2 24 — Analog ground (internal bias)
AGND3L 27 — Analog ground (left channel DACFF)
AGND3R 16 — Analog ground (right channel DACFF)
BCK 6 I Bit clock input (1)
DATA 5 I Serial audio data input (2)
DGND 8 — Digital ground
IOUTL+ 25 O Left channel analog current output+
IOUTL– 26 O Left channel analog current output–
IOUTR+ 17 O Right channel analog current output+
IOUTR– 18 O Right channel analog current output–
IREF 20 — Output current reference bias pin
LRCK 4 I Left and right clock (fS) input (2)
MC 12 I Mode control clock input(2)
MDI 11 I Mode control data input (2)
MDO 13 I/O Mode control readback data output (3)
MS 10 I/OI Mode control chip-select input (4); active low
MSEL 3 I I2C/SPI select (2); active low SPI select
RST 14 I Reset (2); active low
SCK 7 I System clock input(2)
VCC1 23 — Analog power supply, 5 V
VCC2L 28 — Analog power supply (left channel DACFF), 5 V
VCC2R 15 — Analog power supply (right channel DACFF), 5 V
VCOML 22 — Left channel internal bias decoupling pin
VCOMR 21 — Right channel internal bias decoupling pin
VDD 9 — Digital power supply, 3.3 V
ZEROL 1 I/O Zero ag for left channel (4)
ZEROR 2 I/O Zero ag for right channel (4)
(1) Schmitt-trigger input, 5-V tolerant.
(2) Schmitt-trigger input, 5-V tolerant.
(3) Schmitt-trigger input and output. 5-V tolerant input. In I2C mode, this pin becomes an open-drain 3-state output;
otherwise, this pin is a CMOS output.
(4) Schmitt-trigger input and output. 5-V tolerant input and CMOS output.
PIN CONFIGURATIONS
SYMBOL DESCRIPTION
CS# Chip Select
SI/SIO0
Serial Data Input (for 1 x I/O) / Serial Data
Input & Output (for Dual Output mode)
SO/SIO1
Serial Data Output (for 1 x I/O) / Serial
Data Output (for Dual Output mode)
SCLK Clock Input
WP# Write Protection
HOLD#
Hold, to pause the device without
deselecting the device
VCC + 3.3V Power Supply
GND Ground
PIN DESCRIPTION
8-PIN SOP (150/200mil)
8-LAND, WSON (6x5mm)
8-PIN PDIP (300mil)
1
2
3
4
CS#
SO/SIO1
WP#
GND
8
7
6
5
VCC
HOLD#
SCLK
SI/SIO0
1
2
3
4
CS#
SO/SIO1
WP#
GND
VCC
HOLD#
SCLK
SI/SIO0
8
7
6
5
8-LAND USON (2x3mm)
1
2
3
4
CS#
SO/SIO1
WP#
GND
8
7
6
5
VCC
HOLD#
SCLK
SI/SIO0
1
2
3
4
CS#
SO/SIO1
WP#
GND
8
7
6
5
VCC
HOLD#
SCLK
SI/SIO0
PIN CONFIGURATION
ZEROL
ZEROR
MSEL
LRCK
DATA
BCK
SCL
DGND
V
DD
MS
MDI
MC
MDO
RST
V 2L
CC
AGND3L
IL
OUT
I L+
OUT
AGND2
V1
CC
VL
COM
VR
COM
I
REF
AGND1
IR
OUT
I R+
OUT
AGND3R
V 2R
CC
1 2 3 4 5 6 7 8 9
10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
PCM1795
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........................................................................................................................................................................................................ SLES248 – MAY 2009
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SSOP-28
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Table 1. TERMINAL FUNCTIONS
TERMINAL
NAME NO. I/O DESCRIPTION
AGND1 19 — Analog ground (internal bias) AGND2 24 — Analog ground (internal bias) AGND3L 27 — Analog ground (left channel DACFF)
AGND3R 16 — Analog ground (right channel DACFF) BCK 6 I Bit clock input
(1)
DATA 5 I Serial audio data input
(2)
DGND 8 — Digital ground
I
OUT
L+ 25 O Left channel analog current output+
I
OUT
L– 26 O Left channel analog current output–
I
OUT
R+ 17 O Right channel analog current output+
I
OUT
R– 18 O Right channel analog current output–
I
REF
20 — Output current reference bias pin
LRCK 4 I Left and right clock (f
S
) input
(2)
MC 12 I Mode control clock input
(2)
MDI 11 I Mode control data input
(2)
MDO 13 I/O Mode control readback data output
(3)
MS 10 I/OI Mode control chip-select input
(4)
; active low
MSEL 3 I I
2
C/SPI select
(2)
; active low SPI select
RST 14 I Reset
(2)
; active low
(1) Schmitt-trigger input, 5-V tolerant.
(2) Schmitt-trigger input, 5-V tolerant.
(3) Schmitt-trigger input and output. 5-V tolerant input. In I
2
C mode, this pin becomes an open-drain 3-state output; otherwise, this pin is a
CMOS output.
(4) Schmitt-trigger input and output. 5-V tolerant input and CMOS output.
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