Denon S-101 - Display Controller M66005-0001 AHP; Block Diagram; Terminal Functions

23
S-101
M66005-0001AHP (IC301: 1U-3681)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
M66005-0001AHP
V
p
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG00
SEG01
SEG02
Vcc2
DIG15/SEG39
DIG14/SEG38
DIG13/SEG37
DIG12/SEG36
DIG09
DIG10
DIG11
DIG06
DIG07
DIG08
DIG04
DIG05
14
15
16
CGROM
(35bit x 160)
CGRAM
(35bit x 16)
code
write
data
dot data
write
code
select
timing
clock
59
33
31
23
64
63
62
61
DIG12/
SEG36
DIG13/
SEG37
DIG14/
SEG38
DIG15/
SEG39
SEG00
SEG26
.
.
.
SEG27
SEG35
.
.
.
.
.
.
.
.
.
12
1
DIG00
DIG11
.
.
.
.
.
.
scan pulse
CS
SCK
SDATA
21
20
XIN
XOUT
13
RESET
BLOCK DIAGRAM
.
.
.
.
.
.
.
.
.
18
17
2
P0
P1
19
60
22
32
Vcc1
Vcc2
Vss
V
p
Serial
receive
circuit
Code/
command
control
circuit
Bank 1 : 8bit x 16
Bank 2 : 8bit x 64
Display code RAM
Segment
output
circuit
Segment/
Digit
select/
output
circuit
Digit
output
circuit
Clock
generator
Display
controller
24
SEG34
・
・
・
・
・
・
・
・
・
・
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
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