Denon S-101 - Audio ICs BH7868 FS and LC72720 NM; BH7868 FS Diagram and Pin Functions; LC72720 NM Diagram and Pin Functions

32
S-101
BH7868FS (IC301, 302: 1U-3695)
LC72720NM (IC506: 1U-3694)
Vcc1
S1
S2
CIN
MUTE1
CVIN
SEL (CV/MIX)
YIN
BIAS
SEL (BIAS/CLAMP)
Py/G IN
GND
Pb/B IN
MUTE2
Pr/R IN
Vcc2
COUT
S-DCOUT
CVOUT
CVOUT
GND
YOUT
YOUT SAG
GND
Py/G OUT
Py/G OUT SAG
GND
Pb/B OUT
Pb/B OUT SAG
GND
Pr/R OUT
Pr/R OUT SAG
1
2
3
4
5'
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
75Ω
75Ω
6dB
Bias
Bias
Bias
Bias
6dB
Clamp
6dB
Clamp
Clamp
MUTE1
MUTE2
H
L
6MHz
LFP
S-DCOUT
LPF
6MHz
LFP
75Ω
6MHz
LFP
75Ω
L
H
12MHz
LFP
6dB
75Ω
12MHz
LFP
6dB
Bias
75Ω
12MHz
LFP
6dB
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
Vref
MPXIN
Vdda
Vssa
FLOUT
CIN
T1
T2
T3 (RDCL)
T4 (RDDA)
T5 (RSFT)
XOUT
SYR
CE
DI
CL
DO
RDS-ID
SYNC
T7 (CORREC/ARI-ID/BEO)
T6 (ERROR/57K/BE1)
Vssd
Vddd
XIN
REFERENCE
VOLTAGE
ANTIALIASING
FILTER
57kHz
BPF
(SCF)
SMOOTHING
FILTER
PLL
(57kHz)
CLOCK
RECOVERY
(1167.5Hz)
RAM
(24 BLOCK DATA)
ERROR CORRECTION
(SOFT DECISION)
DATA
DECODER
SYNC/EC CONTROLLER
CCB
TEST
VREF
VREF
MEMORY CONTROL
OSC/DIVIDER
SYNC
DETECT-1
SYNC
DETECT-2
CLK(4.332MHz)
FLOUT
CIN
Vdda
Vssa
MPXIN
DO
CL
DI
CE
T1
T2
T3 T7
XIN XOUT
Vddd
Vssd
RDS-ID
SYNC
SYR
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
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