Denon S-301 - Page 60

60
S-301
MX29LV160BTC (IC102: 1U-3692)
39 DSIFL I − 3.3V DSD data input: front left-channel
40 DSIFR I − 3.3V DSD data input: front right-channel
41 DSICT I − 3.3V DSD data input: center channel
42 DSISW I − 3.3V DSD data input: subwoofer channel
43 DSISL I − 3.3V DSD data input: surround left-channel
44 DSISR I − 3.3V DSD data input: surround right-channel
45 DIRDSCK I PD 3.3V
DSBCK I/O select
L: input (slave), H: output (master)
46 SYNC I S, PU 3.3V Forced synchronization input (active-HIGH edge)
47 INIT I S, PU 3.3V Initialization input: Active-LOW, Resync on “L” → “H”
48 VSS −− −Ground
1. S = Schmitt, PU = pull-up resistor, PD = pull-down resistor, mA = output current
No. Name I/O Property
1
Input
voltage
Description
DQ3
DQ9
DQ2
A6
DQ0
W
A3
RB
DQ6
A8
A9
DQ13
A17
A10 DQ14
A2
DQ12
DQ10
DQ15A–1
V
CC
DQ4
DQ5
A7
DQ7
NC
NC
AI06850
M29W160ET
M29W160EB
12
1
13
24 25
36
37
48
DQ8
NC
A19
A1
A18
A4
A5
DQ1
DQ11
G
A12
A13
A16
A11
BYTE
A15
A14
V
SS
E
A0
RP
V
SS
A0-A19 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
DQ8-DQ14 Data Inputs/Outputs
DQ15A–1 Data Input/Output or Address Input
E
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset/Block Temporary Unprotect
RB
Ready/Busy Output
BYTE
Byte/Word Organization Select
V
CC
Supply Voltage
V
SS
Ground
NC Not Connected Internally
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
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