www.dfi .comChapter 3 Hardware Installation
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Chapter 3
Signal Pin# Pin Type Pwr Rail /Tolerance CH960 PU/PD Module Base Specification R2.1 Description COM Express Carrier Design Guide R2.0 Description
I2C_CK B33 I/O OD CMOS 3.3V Suspend/3.3V PU 2.2K to 3.3V Suspend General purpose I2C port clock output General Purpose I2C Clock output
I2C_DAT B34 I/O OD CMOS 3.3V Suspend/3.3V PU 2.2K to 3.3V Suspend General purpose I2C port data I/O line General Purpose I2C data I/O line.
Signal Pin# Pin Type Pwr Rail /Tolerance CH960 PU/PD Module Base Specification R2.1 Description COM Express Carrier Design Guide R2.0 Description
SPKR B32 O CMOS 3.3V / 3.3V
Output for audio enunciator - the "speaker" in PC-AT systems.
This port provides the PC beep signal and is mostly intended for
debugging purposes.
Output used to control an external FET or a logic gate to drive
an external PC speaker.
WDT B27 O CMOS 3.3V / 3.3V PD 100Kɏ Output indicating that a watchdog time-out event has occurred. Output indicating that a watchdog time-out event has occurred.
FAN_PWMOUT B101 O CMOS 3.3V / 12V RSV PD 100Kɏ to GND
Fan s
eed control. Uses the Pulse Width Modulation
ue to
control the fan's RPM.
Fan s
eed control. Uses the Pulse Width Modulation
ue to control the fan’s RPM.
FAN_TACHIN B102 I OD CMOS 3.3V / 12V PU 47Kɏ to 3.3V Fan tachometer input for a fan with a two pulse output. Fan tachometer input for a fan with a two pulse output.
TPM_PP A96 I CMOS 3.3V / 3.3V PD 100Kɏ
to GND.
Trusted Platform Module (TPM) Physical Presence pin. Active high.
TPM chip has an internal pull down. This signal is used to indicate Physical
Presence to the TPM.
Trusted Platform Module (TPM) Physical Presence pin. Active
high. TPM chip has an internal pull down. Thissignal is used to
indicate Physical Presence to the TPM.
Signal Pin# Pin Type Pwr Rail /Tolerance CH960 PU/PD Module Base Specification R2.1 Description COM Express Carrier Design Guide R2.0 Description
PWRBTN# B12 I CMOS 3.3V Suspend/3.3V
PU 10Kɏ to 3.3V Suspend
A falling edge creates a power button event. Power button events can
be used to bring a system out of S5 soft off and other suspend states,
as well as powering the system down.
Power button low active signal used to wake up the system from
S5 state (soft off). This signal is triggered on the falling edge.
SYS_RESET# B49 I CMOS 3.3V Suspend/3.3V PU 10Kɏ to 3.3V Suspend
Reset button input. Active low request for Module to reset and reboot.
May be falling edge sensitive. For situations when SYS_RESET# is
not able to reestablish control of the system, PWR_OK or a power
cycle may be used.
Reset button input. Active low request for Module to reset and
reboot. May be falling edge sensitive. For situations when
SYS_RESET# is not able to reestablish control of the system,
PWR_OK or a power cycle may be used.
CB_RESET# B50 O CMOS 3.3V Suspend/3.3V
PD 100Kɏ to GND
Reset output from Module to Carrier Board. Active low. Issued by
Module chipset and may result from a low SYS_RESET# input, a low
PWR_OK input, a VCC_12V power input that falls below the minimum
specification, a watchdog timeout, or may be initiated by the Module
software.
Reset output signal from Module to Carrier Board. This signal
may be driven low by the Module to reset external components
located on the Carrier Board.
PWR_OK B24 I CMOS 3.3V / 3.3V
Both PU 10Kɏ to 5V and
PD20K
Power OK from main power supply. A high value indicates that the
power is good. This signal can be used to hold off Module startup to
allow Carrier based FPGAs or other configurable devices time to be
programmed.
Power OK status signal generated by the ATX power supply to
notify the Module that the DC operating voltages are within the
ranges required for proper operation.
I2C Si
SUS_STAT# B18 O CMOS 3.3V Suspend/3.3V PD 100Kɏ to GND Indicates imminent suspend operation; used to notify LPC devices.
Sus
nal to indicate that the s
stem will be
entering a low power state soon. It can be used by other
peripherals on the Carrier Board as an indication that they
should
ower-down mode.
SUS_S3# A15 O CMOS 3.3V Suspend/3.3V PD 100Kƻ to GND
Indicates system is in Suspend to RAM state. Active low output. An inverted
copy of SUS_S3# on the Carrier Board may be used to enable the non-
standby power on a typical ATX supply.
S3 Sleep control signal indicating that the system resides in S3
state (Suspend to RAM).
SUS_S4# A18 O CMOS 3.3V Suspend/3.3V PD 100Kƻ to GND Indicates system is in Suspend to Disk state. Active low output.
S4 Sleep control signal indicating that the system resides in S4
state (Suspend to Disk).
SUS_S5# A24 O CMOS 3.3V Suspend/3.3V PD 100Kƻ to GND Indicates system is in Soft Off state.
S5 Sleep Control signal indicating that the system resides in S5
State (Soft Off).
WAKE0# B66 I CMOS 3.3V Suspend/3.3V PU 1Kɏ to 3.3V Suspend PCI Express wake up signal. PCI Express wake-up event signal.
WAKE1# B67 I CMOS 3.3V Suspend/3.3V
PU 10Kɏ to 3.3V Suspend
General purpose wake up signal. May be used to implement wake-up
on PS2 keyboard or mouse activity.
General purpose wake-up signal.
BATLOW# A27 I CMOS 3.3V Suspend/ 3.3V PU 10Kƻ to 3.3V Suspend
Indicates that external battery is low.
This port provides a battery-low signal to the Module for orderly
transitioning to power saving or power cut-off ACPI modes.
Battery low input. This signal may be driven low by external
circuitry to signal that the system battery is low. It also can be
used to signal some other external power management event.
LID# A103 I OD CMOS 3.3V Suspend/12V
PU 47Kɏ to 3.3V Suspend
LID switch. Low active signal used by the ACPI operating system for a LID
switch.
LID switch.
Low active signal used by the ACPI operating system for a LID
switch.
SLEEP# B103 I OD CMOS 3.3V Suspend/12V
PU 47Kɏ to 3.3V Suspend
Sleep button. Low active signal used by the ACPI operating system to bring
the
system to sleep state or to wake it up again.
Sleep button.
Low active signal used by the ACPI operating system to bring the
system to sleep state or to wake it up again.
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