Quad Primitive Pin type Pin DisplayPort signal
118 GTXE2_CHANNEL X0Y12 MGTXTXP/N0 D2/D1 Source Lane 0
MGTXRXP/N0 E4/E3 Sink Lane 0
X0Y13 MGTXTXP/N1 C4/C3 Source Lane 1
MGTXRXP/N1 D6/D5 Sink Lane 1
X0Y14 MGTXTXP/N2 B2/B1 Source Lane 2
MGTXRXP/N2 B6/B5 Sink Lane 2
X0Y15 MGTXTXP/N3 A4/A3 Source Lane 3
MGTXRXP/N3 A8/A7 Sink Lane 3
IBUFDS_ X0Y6 MGTREFCLKP/N0 C8/C7 135
MHz ()
Table 17. DisplayPort quad pinout.
The auxiliary channel is a bidirectional LVDS bus. Depending on the Xilinx tool/IP version, instantiating a differential I/O
buffer with LVDS signaling standard might not be possible. The work-around is to have two pairs of pins wired and shorted
together as seen in Figure 19. One pair should be implemented as input-only and the other as output-only.
If the tool/IP allows bidirectional LVDS buffers, only one of the pairs needs to be used (it does not matter which), while the
other declared as input and not used.
The hot-plug detect (HPD) signal connects to a general user I/O pin and should be configured as an input.
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