Digilent Genesys 2 - Page 30

The full implementation details of the DisplayPort standard is outside the scope of this document. Refer to the full
specifications published by VESA for more details. DisplayPort Source and Sink IPs can be licensed separately from Xilinx.
A Univision Technology Inc. UG-2832HSWEG04 is loaded on the Genesys 2. It is a white monochrome, 128 x 32, 0.91”
organic
LED () display matrix bundled with a Solomon Systech SSD1306 display controller. The display data interface towards
the FPGA is a 4-wire serial peripheral interface (SPI). The 4 wires in controller-terminology are
CS ()#, D/C#, SDIN, and
SCLK (), but CS ()# is hard-wired to ground. This adds to the reset and two power control signals for proper start-up
sequencing. The signals are summarized in Table 17.
Signal Description Polarity FPGA Pin
RES# Reset Active-low
CS ()# Chip select (always active) Active-low N/A
D/C# Data (high)/Command (low) Both
SCLK () Serial Clock Active-high
SDIN Serial Data Active-high
VBAT# Power enable for internal power supply Active-low
VDD# Power enable for digital power Active-low
Table 17.
OLED () signal description.
The serial interface is synchronous to
SCLK () and must conform the timing specifications below. In most cases, a 10 MHz ()
SCLK () and data sent on the falling edge should work.
15. OLED
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