3. Instruction Set
MN05003003E For more information visit: www.eaton.com
3-27
High Speed Processing
Mnemonic Availability STEPS
API
16 bits 32 bits
P
Function
PB
B-PB
PC
PA
PH
M-PH
M-PA
PV
16 32
50 REF -
Refresh I/O Immediately
5-
51 REFF -
Refresh and Filter Adjust -
3-
52 MTR - - Input Matrix -
9-
53 - DHSCS - High Speed Counter Set
-13
54 - DHSCR - High Speed Counter Reset
-13
55 - DHSZ - HSC Zone Compare -
-17
56 SPD - - Speed Detection
7-
57 PLSY DPLSY - Pulse Output
713
58 PWM - - Pulse Width Modulation
7-
59 PLSR DPLSR - Pulse Ramp
917
Convenience Instruction
Mnemonic Availability STEPS
API
16 bits 32 bits
P
Function
PB
B-PB
PC
PA
PH
M-PH
M-PA
PV
16 32
60 IST - - Manual/Auto Control
7-
61 SER DSER
Search a Data Stack -
917
62 ABSD DABSD - Absolute Drum Sequencer -
917
63 INCD - - Incremental drum sequencer -
9-
64 TTMR - - Alternate timer -
5-
65 STMR - - Special timer -
7-
66 ALT -
ON/OFF alternate instruction
3-
67 RAMP DRAMP - Ramp signal -
917
68 DTM -
Data transform and move - - -
-9-
69 SORT DSORT - Data sort -
11 21
External I/O Display
Mnemonic Availability STEPS
API
16 bits 32 bits
P
Function
PB
B-PB
PC
PA
PH
M-PH
M-PA
PV
16 32
70 TKY DTKY - 10-key keypad input -
713
71 HKY DHKY - 16-key keypad input -
917
72 DSW - - Digital Switch input -
9-
73 SEGD -
Decode the 7-step display panel
5-
74 SEGL - - 7-step display scan output
7-
75 ARWS - - Arrow keypad input -
9-
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