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Using BIOS
Advanced Chipset Features
These items define critical timing parameters of the motherboard. You should leave the
items on this page at their default values unless you are very familiar with the technical
specifications of your system hardware. If you change the values incorrectly, you may
introduce fatal errors or recurring instability into your system.
Phoenix-AwardBIOS CMOS Setup Utility
Advanced Chipset Features
DRAM Timing Selectable [By SPD]
CAS Latency Time [2]
Active to Precharge Delay [8]
DRAM RAS# to CAS# Delay [4]
DRAM RAS# Precharge [4]
Memory Frequency For [Auto]
System BIOS Cacheable [Disabled]
Video BIOS Cacheable [Disabled]
AGP Aperature Size (MB) [128]
Init Display First [PCI Slot]
** Photon Acceleration Technology **
Fast Chip Select [Auto]
CPC Addr/Control [Auto]
Turbo Mode [Auto]
** On-Chip VGA Setting **
On-Chip Frame Buffer Size [8MB]
Boot Display [Auto]
Item Help
Menu Level
f
: Move Enter: Select +/-/PU/PD:Value F10:Save ESC:Exit F1: General Help
mnlk
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
DRAM Timing Selectable (By SPD)
Enables you to select the CAS latency time in HCLKs of 2, 2.5, or 3. The value is set at the
factory depending on the DRAM installed. Do not change the values in this field unless you
change specifications of the installed DRAM or the installed CPU.
CAS Latency Time (2)
This item controls the timing delay (in clock cycles) before the DRAM starts a read
command after receiving it.
Active to Precharge Delay (8)
This precharge time is the number of cycles it takes for DRAM to accumulate its charge
before refresh.
DRAM RAS# to CAS# Delay (4)
This field lets you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed. Disabled gives faster performance; and En-
abled gives more stable performance.
Memory Frequency For (Auto)
This item sets the main memory frequency. When you used an external graphics card,
you can adjust this to enable the best performance for your system.
DRAM RAS# Precharge (4)
Select the number of CPU clocks allocated forthe Row Address Strobe (RAS#) signal to
accumulate its charge before the DRAM is refreshed. If insufficient time is allowed,
refresh may be incomplete and data lost.
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