32
- Device ID
PACKAGE
- Lead/Halogen Free
- TSOP48 12 x 20 x 1.2 mm
- FBGA63 9 x 11 x 1.0 mm
b) Description
H27(U_S)2G8_6F2C series is a 256Mx8bit with spare 8Mx8 bit capacity. The device is
offered in 3.0/1.8 Vcc Power Supply, and with x8 and x16 I/O interface Its NAND cell
provides the most cost-effective solution for the solid state mass storage market. The memory
is divided into blocks that can be erased independently so it is possible to preserve valid data
while old data is erased.
The device contains 2048 blocks, composed by 64 pages. Memory array is split into 2
planes, each of them consisting of 1024 blocks. Like all other 2KB - page NAND Flash
devices, a program operation allows to write the 2112-byte page in typical 200us(3.3V) and
an erase operation can be performed in typical 3.5ms on a 128K-byte block.
In addition to this, thanks to multi-plane architecture, it is possible to program 2 pages at a
time (one per each plane) or to erase 2 blocks at a time (again, one per each plane). As a
consequence, multi-plane architecture allows program time to be reduced by 40% and erase
time to be reduction by 50%. In case of multi-plane operation, there is small degradation at
1.8V application in terms of program/erase time.
The multiplane operations are supported both with traditional and ONFI 1.0 protocols.
Data in the page can be read out at 25ns (3V version) and 45ns (1.8V version) cycle time per
byte. The I/O pins serve as the ports for address and data input/output as well as command
input. This interface allows a reduced pin count and easy migration towards different
densities, without any rearrangement of footprint. Commands, Data and Addresses are
synchronously introduced using CE#, WE#, ALE and CLE input pin. The on-chip
Program/Erase Controller automates all read, program and erase functions including pulse
repetition, where required, and internal verification and margining of data.
A WP# pin is available to provide hardware protection against program and erase operations.
The output pin RB# (open drain buffer) signals the status of the device during each
operation. In a system with multiple memories the RB# pins can be connected all together to
provide a global status signal. Each block can be programmed and erased up to 100,000
cycles with ECC (error correction code) on. To extend the lifetime of Nand Flash devices, the
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