CONFIDENTIAL
2 Schematic Checklist
Note:
1. VDD_SPI voltage is determined either by the strapping value of GPIO45 or by VDD_SPI_TIEH. When
EFUSE_VDD_SPI_FORCE is 0, VDD_SPI voltage is determined by the strapping value of GPIO45; when
EFUSE_VDD_SPI_FORCE is 1, VDD_SPI voltage is determined by VDD_SPI_TIEH.
2. The strapping combination of GPIO46 = 1 and GPIO0 = 0 is invalid and will trigger unexpected behavior.
3. ROM boot messages can be printed over U0TXD (by default) or GPIO17 (U1TXD), depending on the eFuse bit
EFUSE_UART_PRINT_CHANNEL.
4. When both EFUSE_DIS_USB_SERIAL_JTAG and EFUSE_DIS_USB_OTG are 0, ROM boot messages will be printed
to the USB Serial/JTAG controller. Otherwise, the messages will be printed to UART, controlled by GPIO46 and
EFUSE_UART_PRINT_CONTROL. Specifically, when EFUSE_UART_PRINT_CONTROL value is:
0, print is normal during boot and not controlled by GPIO46.
1 and GPIO46 is 0, print is normal during boot; but if GPIO46 is 1, print is disabled.
2 and GPIO46 is 0, print is disabled; but if GPIO46 is 1, print is normal.
3, print is disabled and not controlled by GPIO46.
Figure 10 shows the setup and hold times for the strapping pin before and after the CHIP_PU signal goes high.
Details about the parameters are listed in Table 5.
CHIP_PU
t
HD
t
SU
Strapping pin
V
IL_nRST
V
IH
Figure 10: Setup and Hold Times for the Strapping Pin
Table 5: Parameter Descriptions of Setup and Hold Times for the Strapping Pin
Parameter Description Min (µs)
t
SU
Setup time before CHIP_PU goes from low to high 0
t
HD
Hold time after CHIP_PU goes high 3
2.9 USB
ESP32-S3 has a full-speed USB On-The-Go (OTG) peripheral with integrated transceivers. The USB peripheral is
compliant with the USB 1.1 specification. GPIO19 and GPIO20 can be used as D- and D + of USB respectively.
It is recommended to populate zero-ohm series resistors between the mentioned pins and the USB connector.
Also reserve a footrpint for a capacitor to ground on each trace.
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ESP32-S3 Series Hardware Design Guidelines v1.0