8502A
monostabie multivibrator, U36, and a “D” type flip-flop,
U!4. U36 is
triggered
by AI5 TTL and
SYNC
^
If
DLD ACK does not occur within the time
constant of U3
6,
U36 will dock
UI4 to generate ACK iNT. ACKWitI is
also generated by U14 to
end the wait state resulting
from
the external address.
3-52.
The MARK fNT logic is armed
by
an interna!
address keyed to RAM. A1.5 TTL is high indicating an
internal address. DB4 is high as part of the status word
indicating
an address to
an
output device.
A15 TTL and
DB4 (both higli) with SYNC
<^2 dock
U1 through U3M2.
A14 is
low for a RAM address so Ul-7 is
clocked
high.
Although the address which arms the mark is
keyed
to
RAM, no data transfer takes place between the micropro-
cessor
and RAM. The write signal
(R/W)
is disabled by
OUT
from the STATUS LATCH. MEM RD (memory read)
is
disabled by DBIN (from the microprocessor) and
MEMR
(from
the
ST.\TUS
LATCH)
both being
low. After ARM
MARK (Ul-7) is docked high, the next
pulse
from
the
phase-locked loop timing circuit docks U14
to generate the
MARK INT signal.
3-53. Interrupts are prioritized through
INT VECTOR
(refer
to
Controller schematic, Section
8).
Before entering
a wait state after an
interrupt, the microprocessor puts
out
a DBIN signal, si gnifying that it is ready to
receive data.
DBIN and INTA produce EN INT through U37 to
enable
the Interrupt
Vector
(U28).
Internal interrupts are applied
directly to U28 and
have priorities
of one
(highest) for
ACK
INT and six
(lowest) for MARK
INT. For an
internal
interrupt,
HNT is
generated
by one section of U38
(Figure
3-13)
and,
when
latched into the
Status Latch (U18),
is,
used to end
the wait state. For an external
interrupt, SYN
1I.NT is
low and with EN
INT low, INA is generated on
the
interbus.
The interrupting module must
respond with an
3-11
To Next Page
Loading...
