8502A
ACK and a data bit on IDl-4. The returned ACK ends the
wait state and the data bit is applied to INT VECTOR, U28.
The
complement of the output from
U28
is placed
on
the
data bus to instruct the microprocessor where to go for the
next instruction.
3-54.
Front Panel
3-55.
Annunciator segment data is
clocked
into register
one
by
the direct address, ICO,
1,
5 high. Refer to Figure
3-15.
Data output from the
switch
matrix is also a direct
address—ICO,
1,
6 high. For either direct address, the
condi-
tion of ID7
(high for disable)
is
latched
into U23 to
enable
an indirect address. Digit segment address—ICl, 5 high, and
digit-annunciator select
address—ICO,
5 are both indirect
addresses. Data
is
clocked into the registers upon termina-
tion of the address.
An update sequence
is as
follows:
1. Register one is addressed with all data lines low
to
blank tlie annunciator display and enable indirect
addressing.
2. Register
two
is addressed
indirectly with
data lines
low to blank the digit display.
3.
Register three is addressed indirectly with all data
lines high to
turn off all LEDs, disable the switch
matrix, and
disable indirect addressing.
4. Register one
is
addressed with ID7 low to enable
indirect addressing and with annunciator segment
data on IDO-6. The data is latched and applied to
the
annunciator LEDs.
5. Reg^ter
two is addressed with
digit segment data
on
IDO-7 (U23
is not
clocked
by
this address so
ID7 may be high without disabling
indirect ad-
dressing).
The
data is
latched and applied to the
digit LEDs.
6.
Register
three
is
addressed with ID7 high (disable
indirect
addressing) and one of the data lines,
IDO-6, low to
enable one digit
LED
and one an-
nunciator
LED.
One
bank of the switch
matrix is
also enabled.
7.
The output buffer is addressed enabling the data
from the previously enabled switch bank
to be
placed
on
the data bus. One or more lines low
indicates a
change
is
desired. This address also
keeps
the kill circuit charged.
3-56. The seven steps just outlined
are required for one
digit-annundator-switch
bank update. The process is re-
peated seven times for a
complete update. The kill circuit
is used to
blank the display if the Controller
discontinues
addressing the front panel.
Otherwise, segments would be
left on continuously and
would soon bum out.
3-57.
DC
Signal Conditioner
3-58.
Relays K1 and K2 control
the
input to
the
DC Sig-
nal Conditioner and the attenuation of the input (Figure
3-16). If both relays are energized,
the
input is from the
Volt/n input terminals with
—
64
attenuation. If
just Kl is
energized, the input
is from the Volt/fi input terminals
with
no
attenuation. If
just K2 is
energized,
the input is
from RTI (optional
signal
conditioners).
QIO, Qll, CRB,
and
CR4
provide overvoltage
protection.
3-59.
A
differential
amplifier
(Q18,
Q19)
drives
U3.
FET
switches
(Q14, Q15, Q16)
control the gain
of
Q18,
and
Q37. An output
voltage
swing of±20V
is achieved
through bootstrapping; U4 provides a bootstrap
for
Q33
and Q37,
and U3 and U4 provide a bootstrap
for U5 and
U6.
Current sink and source for
Q18
and
Q19 are
provided
by Q33
and
Q37
respectively.
3-60. The DC Signal Conditioner is addressed by ICO,
3,
4 high. Data on
lDO-3
is
latched up and decoded to deter-
mine which
switches
and relays
will be energized. Figure
3-16
includes an
example
of the
relay driver used
to
mini-
mize thermal changes in the relays between the on and off
states. RC coupling
between the decoder
and
the relay
driver provide voltage swings up to 4V or down to OV to
ensure positive relay action. Steady state voltages of 1
.45V
(off) and
2.75V
(on)
minimize current differences between
the on and off states while maintaining the relay state
under all conditions.
3-61.
Filter/External Reference
3-62. All inputs to the A/D
Converter are
routed
through the
Filter/Extemal Reference module. Refer to
Figure
3-17. External
reference measurements are
made
by
multiplexing the
three
Filter module inputs to the A/D
Converter.
Q18,
Q19,and
Q20
switch the signal conditioner
input, the external reference
LO
input,
and the external
reference HI input respectively. Data controlling the
switches
is
latched into U1
upon
termination
of
the address
(ICl,
3,
4 high).
3-63. Three-pole, active
Bessel filters (U3 and U4) have
different settling times and cut-off points. Either filter may
be
selected from the front input panel for application
to
the
signal conditioner
input.
Bypass
is
automatically selected
for
external reference inputs or may be remotely selected
for signal
conditioner inputs. The
combination of
Q32,
Q25, Q23, Q24,
or
Q21,
Q22 is turned
on to
select
a
filter
mode.
3-64.
A dual, super-beta transistor in a differential con-
figuration
(Q27)
drives
U5. A
current
source
(Q26)
and
sink
(030)
bias Q27. Enough current is drawn through
R19 by Q26
to bootstrap the input amplifier,
Q27,
5V
above the output. Gain of the amplifier is set at one by the
combination of R21 and the input resistors.
The
external
reference inputs have additional
series
resistors
located at
the rear panel
terminals.
3-12
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