8
1.5 RECEIVING CIRCUIT
The received signal is amplified by the Log Amplifier Circuit. Both 200 and 50 kHz RX circuits
are located on the ANLG board and the one of RX circuits is selected by U9 in accordance with
the System Menu 3 setting.
Figure 1.7 shows the receiving amplifier circuit.
Gain Control Circuit
Figure 1.8 shows the gain control circuit. The gain VR setting is detected by the CPU as binary
code data "000 to 255" which is converted to DC gain control voltage by the A/D converter U5.
The gain control voltage ( 1.9 to 3.8V ) controls the amplitude of Q16/Q21 in the receiving
circuit.
Figure 1.8 Gain control circuit
Figure 1.7 Receiving amplifier circuit on the ANLG board
1.9V to 3.8V
1.5 RECEIVING CIRCUIT
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