5.4 Block Description
5-20
TCXO
TCXO(Temperature Compensate Crystal Oscillators) PLL reference frequency and of
TX/RX board and DUP RX board is created based on TCXO of Y1: 25.6 MHz/+5ppm.
There is no specific part where frequency is adjusted. If TX frequency tolerance is over
+10 ppm, replace CPU board or TCXO. 38.4 MHz is created by multiplying 25.6 MHz
by 3 on Q10 and is divided by 2 on U33. Frequency gained through this is used for
clock of DSP (CLK Max. 50 MHz).
Fig. 5.4.15 Standard Oscillation Circuit
MODULATION
Below block diagram shows the process where modulation is carried out in DSP.
Pre-emphasisLPF
FSK MOD
SEL
Calculation:
DDS setting data
DDS setting
data output
U25: DDS
50kHz
45MHz
50kHz 8.3kHz
50kHz
300kHz
50kHz
Calculation:
FSK data(B/Y)
U10: CODEC
U20: DSP
LINE IN
Handset MIC
Wing Hanset
A/D
SDATA OUT
U30:
CPU
Control
Control
FSK data(0/1)
Voice Data
Pre-emphasis
Enable/unenable
DDS Fo Select
Select
Fig. 5.4.16 Modulation Process
x3
TX/RX
05P0774
DUP RX
05P0777
TCXO
Y1:
25.6 MHz
U37
U37
25.6MHz
25.6MHz
25.6MHz
25.6MHz
45MHz
J13
U37
U37Q10
38.4MHz
For DSP CLK: 38.4MHz
J3
J11
CH70 RX
05P0775
J1
J7
J8
J2
1/2
U33
U37
Divider
For CLK
- CPU
- DSP
- DDS
- CODEC
For 2nd Lo
For PLL Ref.
For PLL Ref.
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