Furuno FS-1570 - Function of CPU; Memory

5.3 T-CPU board (05P0732)
5-12
5.3.1 Function of CPU
Three CPUs, 32-bit MAIN CPU, 8-bit SUB CPU-1 (I/O) and 8-bit SUB CPU-2 (I/O)
work as shown in Table 5.3.1.
Table 5.3.1 Function of CPU
CPU Function
MAIN CPU
(U3, MB91101)
1) Communicates with SUB CPU-1, SUB CPU-2, FS-2570C, MIF
interface units and DMC
2) Encoding and decoding of DSC and NBDP messages
3) Decides the timing for NBDP communication
4) Interfaces with DSC DSP and NBDP DSP
5) Reads check signals
6) Controls external BK, antenna coupler and IC-302/IC-303-DSC
7) Receives NMEA signal
SUB CPU-1 (I/O)
(U8, M38881M2)
1) Communicates with Main CPU
2) Interfaces with Incoming Indicator, No.1 and No.2 FS-2570C
3) Detects the absence of W/R1 and W/R 2
SUB CPU-2 (I/O)
(U15, M38881M2)
1) Communicates with Main CPU
2) Interfaces with IEC61162 device, DMC-5, IC-302-DSC, NBDP
DSP and MIF devices
5.3.2 Memory
Table 5.3.2 shows the memory contents.
Table 5.3.2 Memory contents
Memory Contents
8 Mbit Flash ROM
(U4, MBM29F800TA)
1) RT, DSC and NBDP programs
2) Default settings of DSC system setup menu
3) Default settings of RT system setup menu
4) ITU channels
256 kbit EEPROM
(U5, AT28C256)
1) Settings of DSC system setup menu
2) Settings of RT system setup menu
3) MMSI and model
4) User channels
5) Communication log
1 Mbit SRAM
(U6 and U7, K6T1008C2E)
Used by MAIN CPU as working memory