Furuno FS-1570 - Page 135

5.3 T-CPU board (05P0732)
5-18
Table 5.3.6 Signals generated by DATA 2 on W/R1 board
W/R1
Pin No.
& Name
Order of
execution
Signal name Function
U502 PLL data PLL data for PLL IC (U502)
#15 QA 1 DDS2 LOAD A
LOAD signal for U506 (DDS2, 456.7
kHz)
#1 QB 2 DDS1 LOAD B
LOAD signal for U501 (DDS1, 6 MHz
PLL Ref)
#2 QC 3
U503 ST
(NOR: ST CONT2)
Used to generate latch signal for U503
by NOR gate ST CONT2 signal
#3 QD 4
U502 ST
(NOR: ST CONT2)
Used to generate latch signal for U502
by NOR gate ST CONT2 signal
#4 QE 5 N.C
#5 QF 6 N.C
#6 QG 7 N.C
U504
#7 QH 8 N.C
#16 Q1 9 BAND-1 PLL BAND selection (1.6 to 6 MHz)
#15 Q2 10 BAND-2 PLL BAND selection (6 to 13.5 MHz)
#14 Q3 11 BAND-3
PLL BAND selection
(13.5 to 21.5 MHz)
#13 Q4 12 BAND-4
PLL BAND selection
(21.5 to 27.5 MHz)
#12 Q5 13 H/L Divides each band into 2 bands
#11 Q6 14 TEST Outputs W/R-1 self-test signal (18 MHz)
#10 Q7 15 LPF 1 RF filter selection (1.6 to 13.2 MHz)
U503
#9 Q8 16 LPF 2 RF filter selection (13.2 to 27.5 MHz)
Control signals generated by Data 3 on W/R 2 board are the same as those on
W/R 1 board.