4-56 120 Series Maternal/Fetal Monitor Revision B
2015590-001
Theory of Operation: UA/FECG Board
Table 4-22. Front End Motherboard Connector J3
Pin Number Signal Name Signal Description
1 +5V +5 V Logic Supply
2 BD6 Status/Control Bus Bit 6
3 BD7 Status/Control Bus Bit 7
4 CSO* Status/Control Bus Chip Select 0
5 CS1* Status/Control Bus Chip Select 1
6 CS2* Status/Control Bus Chip Select 2
7 CS3* Status/Control Bus Chip Select 3
8 +5V +5 V Logic Supply
9 BRD* Status/Control Bus Read Line
10 BA1 Status/Control Bus Address Line Bit 1
11 RES* Reset Line
12 RESFR* Unused
13 No Connection —
14 72KHZ 72 kHz Sync Clock
15 +5V +5 V Logic Supply
16 No Connection —
17 +5V +5 V Logic Supply
18 IUP CLK IUP Clock
19 CVRT* IUP Start Conversion Line
20 IUP DATA IUP Serial Data
21 AGND Analog Ground
22 AGND Analog Ground
23 –15V –15 V Supply
24 –15V –15 V Supply
25 AGND Analog Ground
26 AGND Analog Ground
27 –15V –15 V Supply
28 AGND Analog Ground
29 — —
30 — —
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