GE Marquette MAC 5000

Revision B5-4
CPU Theory of Operation: General Description
MAC 5000 resting ECG analysis system
2000657-002
Block Diagram
See Chapter 7, “PCB Assemblies” for references on the CPU schematic.
SA-110
S
TRONGARM
CPU
(Sh2)
Memory
(Sh3)
DRAM
Address
Mux
(Sh2)
4 MEG
EDO
DRAM
(Sh2)
RA0-9
12
5
FPGA
DRAM
Controller
Bootstrap
Unloader
XBus
Controller
"Curly"
68HC705
(Sh2)
BBUS
I/F
Analog
Audio
TPH I/F
Acq Module
I/F
S
TRONGARM Address Bus
S
TRONGARM Data Bus
VGA
LCD
Controller
(Sh2)
A0-8
MAD0-15
EEPROM I/F
VLB Bus I/F
MD1322-011L