Revision B
iv
MAC 5000 resting ECG analysis system
2000657-002
Writer Tests ..................................................................................... 4-19
C-Scan Test 1
C-Scan Test 2
C-Scan Test 3 ..................................................................... 4-19
50 mm/s Test Pattern I
25 mm/s Test Pattern I
5 mm/s Test Pattern I ......................................................... 4-19
Roller Test .......................................................................... 4-20
Test Pattern II ..................................................................... 4-20
Test Pattern II Continuous .................................................. 4-20
Continuously Run Out Paper .............................................. 4-20
Battery Tests .................................................................................... 4-20
Battery Status ..................................................................... 4-20
Battery Discharge Test ....................................................... 4-21
Battery Charge Test ............................................................ 4-21
Print Discharge Test Results
Print Charge Test Results ................................................... 4-21
Communication Tests ...................................................................... 4-21
COM Port Loopback Test .................................................... 4-21
Modem Test ....................................................................... 4-22
Acq. Module Tests ........................................................................... 4-22
Analog I/O Tests .............................................................................. 4-22
Analog Output Test ............................................................. 4-22
Analog Input Test ............................................................... 4-22
DCOut Loopback Test ......................................................... 4-22
Floppy Drive Tests ........................................................................... 4-22
5 CPU Theory of Operation ................................. 5-1
General Description .................................................................. 5-3
Block Diagram ................................................................................... 5-4
Theory of Operation .................................................................. 5-6
Clocks ................................................................................................ 5-6
CPU .................................................................................................... 5-6
FPGA .................................................................................................. 5-6
Bootstrap Instruction Unpacker ............................................ 5-7
EDO DRAM Controller .......................................................... 5-7
XBus Controller .................................................................... 5-7
LCD Controller VLB Bus Cycle Interface ............................... 5-7
Video Waveform Scrolling .................................................... 5-8
Interrupt Controller ............................................................... 5-9
System Interrupt Generator .................................................. 5-9
Acquisition Module Interface ................................................ 5-9
Thermal Printhead Interface ............................................... 5-10