GE UR series

5-114 L60 Line Phase Comparison System GE Multilin
5.5 GROUPED ELEMENTS 5 SETTINGS
5
Figure 5–46: OVERALL PHASE COMPARISON LOGIC
87PC phase comparison scheme logic
Force keying
OR
RUN
AND
SETTINGS
= Enabled
CHARGING CURRENT COMP
Off=0
CHARGE COMP BLOCK
L5 phase VT bank: VA
87PC VOLTAGE SOURCE
L5 phase VT bank: VB
L5 phase VT bank: VC
SETTING
F1 phase CT bank: IA
87PC SIGNAL SOURCE
F1 phase CT bank: IB
F1 phase CT bank: IC
L1 phase CT bank: IA
L1 phase CT bank: IB
L1 phase CT bank: IC
Two sources current
One source current
SETTING
87PC LINE XCO & XC1
RUN
Compute charging
current
Breaker-and-a-half logic
Breaker 2
I_2–K×I_1
or 3I_0
Mixing network
87PC V2 FDL OP
87PC dI1/dt FDL OP
87PC FDL AUX OP
87PC dI2/dt FDL OP
87PC IOC FDL OP
87PC I_2 FDL OP
87PC I_1 FDL OP
OPEN BKR ECHO PKP
FLEXLOGIC OPERAND
SETTING
Off = 0
87PC STOP TX
SET TING
Off=0
87PC FDH SUPV
Off=0
AND
AND
200 ms
0
OR
AND
AND
SETTINGS
= Enabled
= Disabled
87PC FUNCTION
Off=0
87PC BLOCK
Off=0
831017AE.CDR
Transmit
logic
87PC TX2 P
87PC TX1 N
87PC TX2 N
87PC TX1 P
L60 CT/VT MODULE
RUN
Breaker-and-a-half logic
Breaker 1
I_2–K×I_1
or 3I_0
Mixing network
Channel 1: from carrier #1
Channel 2: from carrier #2
Rx1P
Rx1N
Rx2P
Rx2N
87PC RX1 N
87PC RX2 P
87PC RX2 N
87PC RX1 P
L60 CT/VT MODULE
V1P > PICKUP
SETTINGS 87PC CH1 RX VOLT 87PC CH2 RX VOLT
V1N > PICKUP
V2P > PICKUP
V2N > PICKUP
87PC FDL OP
FLEXLOGIC OPERANDS
Positive delayed
local pulse
Positive adjusted
remote pulse
Negative adjusted
remote pulse
Negative delayed
local pulse
AND
SETTING
87PC PICKUP DELAY
T
PKP
0
AND
TIMER
AND
SETTINGS 87PC CHNL LOSS
TRIP WINDOW
87PC STABILITY ANGLE 87PC ENHANCED STAB ANGLE 87PC TRIP SECURITY 87PC SECOND COINCID
TIMER
dt T .>
STAB. ANG
Positive-half integrator
dt T .>
STAB. ANG
Negative-half integrator
SETTING
87PC RESET DELAY
0
T
RST
AND
SETTING
87PC TRANS BLOCK
T
RST
T
PKP
87PC TRANS BLOCK OP
FLEXLOGIC OPERANDS
87PC PKP
87PC DPO
87PC OP
SETTING
=Off
87PC HIGH-SPEED
TRIP CONTACT 1
SETTING
=Off
87PC HIGH-SPEED
TRIP CONTACT 2
OR
SETTINGS
87PC SIGNAL
87PC MIXED SIGNAL K 87PC FDL PICKUP 87PC FDL AUX 87PC FDH PICKUP
87PC SCHEME SELECT
87PC FDH AUX 87PC SYMMETRY CH1 87PC SYMMETRY CH2 87PC CH1 DELAY 87PC CH2 DELAY
87PC MIXED SIG REF ANG
TIMER
200 ms
0
87PC V2 FDH OP
87PC dI1/dt FDH OP
87PC FDH AUX OP
87PC dI2/dt FDH OP
87PC IOC FDH OP
87PC I_2 FDH OP
87PC I_1 FDH OP
OR
87PC FDH OP
Σ(I_2 – K × I_1) or 3I_0
BKR1 POS
BKR1 NEG
BKR2 POS
BKR2 NEG
SETTING
87PC TX RESET DELAY
0
T
RST
TIMER
100 ms
0
Reset T to 0
RST