If the first bit and the last bit are BOTH HIGH, the decimal digit
must be a “9”. To identify “999”, six bits must be checked.
For the High power mode BCD output, these are bits H1 and
H4, H5 and H8, and H9 and H12. If these six bits are all HIGH
the decimal number is “999”. WhenallsixbitsareHIGHa
logic LOW “inhibit” signal is needed at the inhibit input of the
up counter control gate.
An 8-input NANDgate,U3, is used for the “HI-HI” inhibit gate.
Three inputs are tied together for the 6-input gate required.
Gates U15 and U27 perform the same function for the “MED-
HI” and “LOW-HI” inhibit functions. (See sheets 3 and 4 of the
Controller schematic).
P.6.13.3 Power Limit Jumpers
The maximum LOW power setting may be limited to one-quarter
power by setting JP5 to position 2-4 and JP6 to position 1-3. The
maximum MEDIUM power setting may be limited to one-half
power by setting JP3 and JP4 to position 2-4.
P.6.13.4 Up-Down Counter Outputs
Eachup-downcounter has a 4-bit BCD output,representingone
decimal digit of the 3-digit power control signal. The digits are
designated by a letter (H, M or L) indicating the power level,
and a numberindicating thesignificanceofthe bit.Forexample,
the High Power output bits are H1 through H12.
“H1” is the Most significant bit, “H12” is the least significant
bit. H1 through H4 represent the first decimal digit, H5 through
H8, the second, and H9 through H12, the third. Examples:
Decimal BCD Bits:
Number H1-H4
500
678
Up-down counter outputs go to “Inhibit” gate inputs and to
Multiplex inputs.
P.6.14
Multiplex and Output Buffers For BCD
Power Data (U9-U11, U21-U23, and U33-U35)
The multiplex selects the LOW, MEDIUM or HIGH BCD
Power Data output to the Analog Input Board. Multiplex inputs
include the 12-bit BCD data, and three “Address” lines (HIGH,
MEDIUM and LOW).
The multiplex uses one buffer for each bit of all power levels.
P.6.14.1 Tri-state Buffers
Refer to Figure P-5. Tri-state buffers have three output states:
a. HIGH: Output pulled to the + supply
b. LOW: Output pulled to ground
c. OPEN: High Impedance output
The output state is controlled by the “C” input. If “C” is HIGH,
the output logic state is the same as the input logic state: either
HIGH or LOW.
If the “C” input is LOW, the output is effectively an OPEN
CIRCUIT.
Refer to the Controller Schematic Diagram and also to Figure
P-5. Note that for each bit of the BCD digital power data, three
tri-state buffer outputs are tied together. For example, bit H5,
bit M5, and bit L5 buffer outputs are tied together.
Figure P-4. Controller Board, Command Input Circuit
817 2099 027
DX-25U
P-12 888-2297-002 Rev. S: 05-02-97
WARNING: Disconnect primary power prior to servicing.
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