will bring U60-4 LOW. The LOW input to U60C will force
U60-10 HIGH.
P.7.7.1 Interlock Gate circuit
Eachinterlockcircuit output from U60-1orU60-4islogicLOW
when there is an interlock fault. Each output goes to the LED
Board status indicator circuits at J7-37 and J7-35, and to the
“Interlock Gate” circuit U51-11, U60-10, U60-13.
The output of U60-4 is inverted to logic HIGH at U60-10 and
U60-1 isinvertedto logicHIGH atU60-13.Thesesignalsaregated
together by U51 and the output at U51-11 will be logic HIGH if
either circuit indicates a fault. This logic HIGH is fed to U51-10.
The other input to U59-9 is a TYPE 1 Fault input from the LED
Board. During a TYPE 1 Fault or Interlock fault, U51-8 will be
logic HIGH. This HIGH generates a latched OFF command
through Q5-7 and inhibits K2 through U52-8.
The output of U51-8 will go HIGH and energize Q5-7 to
generate a latched OFF command.
P.7.8
Interlock String Operation
An “Interlock String” fault causes a “Door Interlock” fault
indication. To prevent an External Interlock fault from causing
a Door Interlock fault status output, Q9-7 “inhibits” the Inter-
lock String input to the Door Interlock status circuit.
P.7.8.1 “Interlock String” Input
The “Interlock String”input circuit consists of two sections of Q9.
(“Inhibit” transistor Q9-7 will be described later; for now, assume
that it remains OFF; that is, its collector is an open circuit.)
The Interlock Status input is normally a logic “HIGH” input
when interlock relay K3 is energized. The logic HIGH to Q9-9
turns the transistor ON and the collector is pulled LOW. This
will turn Q9-13 OFF, and bring the collector HIGH.
P.7.8.2 “Interlock String” Fault
An interlock string failure removes the +30 Vdc input to R87.
Resistor R84 grounds Q9-9 and turns the transistor OFF. The
collectorgoes HIGH, Q9-14 goesLOWto startthe delay timer and
after approximately 0.15 seconds a Door Interlock Fault output is
generated.
P.7.8.3 “Inhibit” Transistor Q9-7
Transistor Q9-7 prevents an “Interlock String” fault caused by
de-energizing External Interlock relay K3 from generating a
“DoorInterlock”status indication. When an“External Interlock
fault-H” input occurs, both “Ext Intlk” input transistor Q8 and
“Inhibit” transistor Q9-7 turn ON. Because Q9-7 is “ON,” it
pulls the collector line LOW, INHIBITING the “Intlk String
Fault-H” input to Q9-13.
P.8 +5B Reset Circuit
The +5B Reset circuit is shown on Sheet 1 of the Controller
schematic diagram, along the top. The circuit uses two sections
of an LP339 low-power comparator.
All circuits supplied from the +5B backup supply are specified
to operate reliably at supply voltages as low as +3 Vdc. If the
+5B supply voltage drops below this value, the +5B RESET
circuit generates two RESET signals: “+5B RESET-L”, a logic
LOW signal and “+5B RESET-H”, a logic HIGH signal. These
signals reset all latch outputs to zero.
The inverting input of comparator U37-1, at pin 6, is a +1.22 Volt
reference voltage from zener diode CR8. The non-inverting input,
at pin 7, is a sample of the +5B voltage from voltage divider
R19-R20. Feedback resistor R32 introduces some hysteresis, so
that the “Fault” outputs occur when the +5B supply drops below
approximately +3.1 Vdc and clear again when the +5B supply
increases above approximately +4.2 Vdc.
P.8.1
+5B Reset-L Output (U37-1)
The output of U37-1 goes LOW when the +5B supply drops
belowthecomparatorthreshold, and providesthe“+5B RESET-
L” logic output.
P.8.2
+5B Reset-H Output (U37-14)
The input to U37-8 is the “+5B RESET-L” signal, and the
non-inverting input is the +1.22 Volt reference. When U37-1
generates a “+5B RESET-L” Fault output, the output of U37-14
goes from zero to approximately the +5B supply voltage. This
output is the “+5B RESET-H” logic signal.
Figure P-8. Control Board "Supply Fault"
(“Regulator Fault”) Circuit, Simplified Diagram (817 1280 097)
Section P - Controller (A38)
Rev. S: 05-02-97 888-2297-002 P-17
WARNING: Disconnect primary power prior to servicing.
To Next Page
Loading...
