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Hitachi 32LD8D20E - Page 8

Hitachi 32LD8D20E
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x 4-level, 24-input interrupt controller
x Patch module for 16 ROM locations
x Two 16-bit reloadable timers
x Capture compare timer for infrared decoding
x Watchdog timer
x Uart
x Real time clock
x PWM units (2 channels 14-bit, 6 channels 8-bit)
x 8-bit ADC (4 channels)
x I2C bus master/slave interface
x Up to 32 programmable I/O ports
5.5 OSD and Teletext Features
The on-chip display unit for displaying Level 1.5 Teletext data can also be used for
customer-defined onscreen displays.
The TVT has an internal XRAM of 32 KB and a BOOT ROM of 4 KB. For operation the
code is fetched from a 16bit FLASH, which can be addressed up to 1 MByte.
In combination with dedicated hardware, the slicer stores TTX data in a VBI buffer of 1
KB. The microcontroller firmware performs all the acquisition tasks (hamming and parity
checks, page search, and evaluation of header control bits) once per field. Additionally,
the firmware can provide high-end Teletext features like Packet-26 handling, FLOF/TOP
and list-pages. The interface-to-user software is optimised for minimal overhead.
5.6 Port Allocation

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