Hitachi DK23DA-20F - 6.4 Interface Signal Timing

K6602705
Rev.3
08.20.01
- 96 -
6.4 Interface Signal Timing
6.4.1 Data Transfer Timing
Figures 6-4, 6-5, and 6-7 show the timing for asserting interface signals for transferring 16-bit and
8-bit data.
Figure 6-4 PIO Data Transfer Timing(Mode 4)
*1 Device Address consists of signals CS0-, CS1-, and DA2-0
*2 Data consists of DD0-15(16 bit) or DD0-7(8 bit)
SYMBOL Description MIN(ns) MAX(ns)
t
0
Cycle Time 120
t
1
Address Valid to DIOR-/DIOW- Setup 25
t
2
DIOR-/DIOW- Pulse Width 70
t
2
i
DIOR-/DIOW- Recovery 25
t
3
DIOW- Data Setup 20
t
4
DIOW- Data Hold 10
t
5
DIOR- Data Setup 20
t
6
DIOR- Data Hold 5
t
6Z
DIOR- Data tristate 30
t
7
Addr Valid To IOCS16- Assertion(MAX) 40
t
8
Addr Valid To IOCS16- Negation (MAX) 30
t
9
DIOR-/DIOW- to Address Valid Hold 10
t
1
t
9
t
7
t
2
t
3
t
5
t
4
t
6
Addr Valid *1
DIOR-/DIOW-
Write Data Valid *2
Read Data Valid *2
IOCS16-
t
8
t
0
t
2i
t
6Z