Rev. 1.71 70 April 11, 2017 Rev. 1.71 71 April 11, 2017
HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Standard Type TM Register Description
OveralloperationoftheStandardTMiscontrolledusingseriesofregisters.Areadonlyregister
pairexiststostoretheinternalcounter10-bitvalue,whilearead/writeregisterpairexiststostore
theinternal10-bitCCRAvalue.Theremainingtworegistersarecontrolregisterswhichsetupthe
differentoperatingandcontrolmodesaswellasthreeCCRPbits.
Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
STM0C0 ST0PAU ST0CK2 ST0CK1 ST0CK0 ST0ON ST0RP2 ST0RP1 ST0RP0
STM0C1 ST0M1 ST0M0 ST0IO1 ST0IO0 ST0OC ST0POL ST0DPX ST0CCLR
STM0DL D7 D6 D5 D4 D3 D2 D1 D0
STM0DH — — — — — — D9 D8
STM0AL D7 D6 D5 D4 D3 D2 D1 D0
STM0AH — — — — — — D9 D8
10-bit Standard TM Register List
STM0C0 Register
Bit 7 6 5 4 3 2 1 0
Name ST0PAU ST0CK2 ST0CK1 ST0CK0 ST0ON ST0RP2 ST0RP1 ST0RP0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
bit7 ST0PAU:STMCounterPauseControl
0:Run
1:Pause
Thecountercanbepausedbysettingthisbithigh.Clearingthebittozerorestoresnormal
counteroperation.WheninaPauseconditiontheSTMwillremainpoweredupandcontinueto
consumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohigh
andresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.
bit6~4 ST0CK2~ST0CK0:SelectSTMCounterclock
000:f
SYS
/4
001:f
SYS
010:f
H
/16
011:f
H
/64
100:f
TBC
101:f
TBC
110:STCK0risingedgeclock
111:STCK0fallingedgeclock
ThesethreebitsareusedtoselecttheclocksourcefortheSTM.Theexternalpinclocksource
canbechosentobeactiveontherisingorfallingedge.Theclocksourcef
SYS
isthesystemclock,
whilef
H
andf
TBC
areotherinternalclocks,thedetailsofwhichcanbefoundintheoscillator
section.
bit3 ST0ON:STMCounterOn/OffControl
0:Off
1:On
Thisbitcontrolstheoverallon/offfunctionoftheSTM.Settingthebithighenablesthecounter
torun,clearingthebitdisablestheSTM.Clearingthisbittozerowillstopthecounterfrom
countingandturnofftheSTMwhichwillreduceitspowerconsumption.Whenthebitchanges
statefromlowtohightheinternalcountervaluewillberesettozero, howeverwhenthebit
changesfromhightolow,theinternalcounterwillretainitsresidualvalueuntilthebitreturns
highagain.IftheSTMisintheCompareMatchOutputModeorthePWMoutputModeor
SinglePulseOutputModethentheSTMoutputpinwillberesettoitsinitialcondition,as
speciedbytheST0OCbit,whentheST0ONbitchangesfromlowtohigh.