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HP 8753D Option 011

HP 8753D Option 011
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5.
The
signal
observ
ed
on
an
oscilloscop
e
should
be
as solid
as the
signal in
Figure 7-4
.
Figure W
AVE7
here.
Figure
7-4.
W
a
v
eform
Integrity
in
SRC
Tune
Mode
6.
The
signal
observ
ed
on
the
sp
ectrum
analyzer
will
app
ear
jittery
as
in Figure
7-5 (b),
not
solid
as
in
Figure
7-5
(a).
This
is
b
ecause
in
SR
C
TUNE
mo
de
the
output
is
not
phase
lo
c
k
ed.
Figure
PLCOMP7
here.
Figure 7-5. Phase Lock
ed Output Compared to Open Loop Output in SRC Tune Mode
7.
Press
4
MENU
5
NNNNNNNNNNNNNNNNN
POWER
to v
ary the p o
wer and c
heck for corresp onding lev
el c
hanges on
the test instrument. (A power change of 20 dB will change the voltage observed on the
oscilloscop e by a factor of ten.)
8. Note the results of the frequency and p ower changes:
If the frequency and p ower output changes are correct, skip ahead to \A12 Reference
Check" lo cated in this chapter.
7-8 Source Troubleshooting DRAFT
3/21/106 15:13
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