as comm
unications b
etw
een the
analyzer and
an
external
con
troller
and/or
p
eripherals.
Figure
12-3
is
a
simplied
blo
c
k
diagram
of
the
digital
control
functional group.
Figure DIBLK12
here.
Figure
12-3.
Digital
Control
Group,
Simplified
Block
Diagram
A1
Front
P
anel
The
A1
fron
t
panel
assem
bly
pro
vides
user
in
terface
with
the
analyzer.
It
includes
the
k
eyb
oard for
lo
cal
user
inputs,
and
the
fron
t
panel
LEDs
that
indicate
instrumen
t
status.
The
RPG
(rotary
pulse
generator)
is
not
electrically
connected
to
the
front
panel,
but
pro
vides
user
inputs
directly
to
the
fron
t
panel
pro
cessor.
A2
Front P
anel
Processor
The
A2 fron
t
panel
pro
cessor
detects
and
deco
des
user
inputs
from
the
fron
t
panel
and
the
RPG,
and
transmits
them
to the
CPU. It
has the
capabilit
y
to
in
terrupt
the
CPU
to
pro
vide
information
up
dates.
It
con
trols
the
fron
t
panel
LEDs
that pro
vide status
information to
the
user.
A9
CPU/A10
Digital
IF
The A9 CPU assem
bly con
tains the main CPU (cen
tral pro
cessing unit), the digital signal
pro cessor, memory
storage, and in
terconnect p ort in
terfaces. The main CPU is the master
controller for the analyzer, including the other dedicated micropro cessors. The memory
includes EEPR
OM, RAM, EPR
OM, and R
OM.
Data from the receiv
er
is serially clo c
ked in
to the A9 CPU assem
bly from the A10 digital IF.
The data taking sequence is triggered either from the A14 fractional-N assem
bly, externally
from the rear panel, or by software on the A9 assembly.
Main CPU
The main CPU is a 16-bit micropro cessor that maintains digital control over the entire
instrument through the instrument bus. The main CPU receives external control information
from the front panel or HP-IB, and p erforms pro cessing and formatting operations on the raw
DRAFT
3/21/106 15:14
Theory of Operation 12-7
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