HP 900 Series - Figure 3-19. RAM Assembly Block Diagram

~
dQ.
::
....
I'D
W
I
""""
~
=
~
cc
00
~
~
00
>
-.....
t:C
-.....
C
~
>
==
>
C1J
C1J
I'D
~
c<
t:C
-
~
0
("')
~
:=
n
~
~
o·
;.
:=
()Q
....
e.
~
t::l
8
('t
U1
n
..,
-5.
~
o·
:=
ex>
co
lower
System Board
Address
Lower
010 II
Address
Upper
System Board
Address
Upper
010 II
Address
RAM
Block
Select
RAM
RAM
Address
Control
/ ~
Signals
t
RAM Block
4,8, or 16MB
32 Bit Wide +
4 Parity Bits
Includes
Buffers & MUX
Write
System
..
Board
~
Select
.-
r Latch 1
~Ir
-
System Board
j~
..
~
Select
010
II
Board
Select
1r
010 II
Select
Parity
Bits
~
..
-
Parity
Check &
Generate
High I Low
Data Dota
Fold
Buffer
50MHz
I-----II .. ~ IR7
Data
- I
Generatl
or
Address
Select
&
Autosize
25 MHz
fram CPU
~=emBoa~
Latch & 010 II
Buffer Data
I
Control
Register
Clock
Circuitry
1--_--1 .. ~ Bus
Clock