HP 9800 SERIES - Page 33

2.2 Theory of Operation
zeo
MICRO-
PROCESSOR
zao DATA BUS
,1L
:II ROM
~---'I-:Sd:"'L~=;;~""T.-t'}'1--I MEMORY
MEMORY MEMORY i..---
"""":"':'::'::":".·:":::::::\Ii ADDRESS
HCONTROL DECODER RAM .--
LINES I-:S:i-ELC-;E"'C""T--t'?:r~RAM
• MEMORY
zeo ADDRESS BUS
IIO CONTROL LINES
bzjZTI:5;ITZ±lZit::EllIz:r;;:~ I/O
.• INTERRUPT
LINES INTER-
k==~--jRUPT
CIRCUIT
ADDRESS
DECODE
-
I/O WRITE \iUN~
IIO READ CONTROL
CLOCK 8 DATA CONTROL
PHI CONTROL
DRIVE CONTROL OUTPUTS
........................... ............. ......... ........... ....... ......................................................... :""':':"':""':"':::'::\:>:::":'{?>
I/O WRITE
REGISTERS
MULTI-
PLEXORS
t
PARALLEL
OUTPUT
LEOS
CRC, READ, WRITE CONTROL LINES
SWITCHES
ERROR INDICATORS
'PHAsE 'lOOPJ+.D!!!AO,!.TA::::..:I.:,oN---j
LOCKEDII+--.---' BACK
LOOP CIRCUllk--,
PLL
CLOCK
I.......-
LQIEIETIj •• p"""Z"""Z"":"Z""':C':':':C':''1:1:9': :': CLOCK AND DATA
DATA I+S~E=R:-:IAc=Lc.:C~L~OC;-,K~IN~_ SEPAR-i--
k-iS;!!;E,QR",IA=-L-,<D",AT.",A'--CIN'-'--_,ATOR
PHI LN ·~~UPTS
HOST SYSTEM kIITITITITITIT2 Hli] I PI BSE C:Z'A\2TIIBL.E2m2IT2IT2IT2IT~
PHI
CHIP
SERIALIZER
~
DE- SERIAL CLOCK OUT I
PARALLEL SERIALIZER HWRITE DATA OUT
1ITl2g?§Ig!Eq SERIAL DATA Jg~~ERATOR ENCODEJ
INPUT OUT
Figure 2.1. Controller Bloc .. Aagram
FLEXIBLE
DISC
DRIVE