5-4 www.hp.com Technical Reference Guide
Input/Output Interfaces
5.4 Diskette Drive Interface
The SFF and CMT form factors support a diskette drive through a standard 34-pin diskette drive
connector. Selected models come standard with a 3.5-inch 1.44-MB diskette drive installed as
drive A.
The diskette drive interface function is integrated into the SCH5317 super I/O component. The
internal logic of the I/O controller is software-compatible with standard 82077-type logic. The
diskette drive controller has three operational phases in the following order:
■ Command phase—The controller receives the command from the system.
■ Execution phase—The controller carries out the command.
■ Results phase—Status and results data is read back from the controller to the system.
The Command phase consists of several bytes written in series from the CPU to the data register
(3F5h/375h). The first byte identifies the command and the remaining bytes define the
parameters of the command. The Main Status register (3F4h/374h) provides data flow control
for the diskette drive controller and must be polled between each byte transfer during the
Command phase.
The Execution phase starts as soon as the last byte of the Command phase is received. An
Execution phase may involve the transfer of data to and from the diskette drive, a mechnical
control function of the drive, or an operation that remains internal to the diskette drive controller.
Data transfers (writes or reads) with the diskette drive controller are by DMA, using the DRQ2
and DACK2- signals for control.
The Results phase consists of the CPU reading a series of status bytes (from the data register
(3F5h/375h)) that indicate the results of the command. Note that some commands do not have a
Result phase, in which case the Execution phase can be followed by a Command phase.
During periods of inactivity, the diskette drive controller is in a non-operation mode known as the
Idle phase.
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