IBM System/370 Guide

10:10 THE CENTRAL PROCESSING UNIT (CPU) AND THE SYSTEM CONSOLE
CENTRAL PROCESSING UNIT
The CPU contains all the elements necessary to decode and execute
the instructions in the System/370 Model 165 instruction set and,
optionally, those in the hardware compatibility feature required by
one of the three 7000-series emulator programs.
The CPU has an 80-nanosecond cycle time and an 8-byte-wide data
path. Extensive parity checking is performed in the CPU to insure
the validity of the data being used. All data transfer, logical, and
arithmetic operations are checked. Automatic hardware retry of most
failing CPU operations, without programming assistance, is provided
as an availability feature and is discussed in the RAS section.
Among the major elements in the CPU are the instruction unit, the
execution unit, local storage, and control storage.
Instruction and Execution Units
The faster internal performance of the Model 165 is due in part
to the use of more concurrence in CPU operations than is implemented
in the Model 65. The Model 165 CPU contains an instruction unit and
an execution unit that overlap instruction fetching and preparation
with instruction execution. The Model 165 instruction unit is
controlled by logic circuits and can process several instructions
concurrently while the execution unit is executing a single instruction.
The instruction unit prefetches instructions (maintaining them in
sequence), decodes instructions, calculates addresses, prefetches
instruction operands, and makes estimates of the success of conditional
branches. When a conditional branch is encountered, the instructions
immediately following the branch and those located at the branch address
are prefetched and placed in separate instruction buffers within the
instruction unit. TWo 16-byte instruction buffers are used. This
insures the availability of prefetched instructions whether the branch
is taken or not.
The execution unit is microprogram controlled and can execute one
instruction at a time. It has the capability of processing a new
instruction every cycle. Emphasis is placed on optimizing fixed binary
and floating-point arithmetic operations. A 64-bit parallel adder
is used to perform binary and floating-point arithmetic, while an 8-
bit serial adder is used in the execution of packed decimal arithmetic.
An imprecise interrupt occurs on a Model 165 only if an attempt
is made to store data at an invalid storage address or at a storage-
protected location.
Local Storage and Control Storage
Local storage contains the general purpose and floating-point
registers and has a read or write cycle time of 80 nanoseconds. It
can be accessed by four sources and written into from one source
simultaneously.
Model 165 control storage consists of a capacitor read-only storage
(ROS) and a monolithic writable control storage eWCS), both of which
have an 80-nanosecond cycle time. ROS and WCS contain all required
microcode for a specific system configuration. ROS contains the
microcode necessary to execute the majority of the Model 165
instructions and some specialized routines. WCS contains the
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IBM System/370 Specifications

General

Brand	IBM
Model	System/370
Category	Server
Language	English