IBM System/370 Guide

Processor Storage
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CPU
Logical
Memory
Instruction
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Buffer
Execution
Bytes
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CPU fetch from buffer - 160 nanoseconds for 8 bytes (2 cycles)
CPU fetch from processor storage - 1.44 microseconds for 8 bytes
(18 cycles)
Buffer fetch from processor storage - 1.44 microseconds for 32
bytes (18 cycles)
Channels to and from processor storage - 32 bytes in a 2 microsecond
cycle
Figure 10.15.3.
conceptual data flow in the
assume no interference.
Times
given
The storage control unit (SCU) contains the high-speed buffer and
controls all buffer and processor storage references made by the CPU,
the channels, and manual controls. The buffer storage control portion
of the SCU handles CPU to processor storage references, both fetches
and stores. Parity checking is used for data verification in the
buffer.
When a data fetch request is made by the CPU, buffer storage control
determines whether or not the requested data is in the high-speed
buffer by interrogating its address array of the buffer's contents.
If the data requested is present in the buffer, it is sent directly
20

IBM System/370 Specifications

General

Brand	IBM
Model	System/370
Category	Server
Language	English